MCQOPTIONS
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MCQOPTIONS
This section includes 289 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Electronics knowledge and support exam preparation. Choose a topic below to get started.
| 51. |
Race around condition always arise in a |
| A. | Combinational circuit |
| B. | Asynchronous circuit |
| C. | Synchronous circuit |
| D. | Digital circuit |
| Answer» C. Synchronous circuit | |
| 52. |
For each of the positive edge-triggered JK flip-flop used in the following figure, the propagation delay is T. |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» C. 3 | |
| 53. |
Consider the following statements: For a Master-Slave JK flip-flop, |
| A. | 1, 2 and 3 |
| B. | 1 and 2 only |
| C. | 2 and 3 only |
| D. | 3 and 4 only |
| Answer» C. 2 and 3 only | |
| 54. |
JK flip-flop can be made from an SR flip-flop by using two additional (A) (B) (C) (D) |
| A. | NAND gates |
| B. | OR gates |
| C. | NOT gates |
| D. | NOR gates |
| Answer» B. OR gates | |
| 55. |
In a JK flip-flop we have J = |
| A. | 010000 |
| B. | 011001 |
| C. | 010010 |
| D. | 010101 |
| Answer» E. | |
| 56. |
A switch tailoring counter is made by using single D-flipflop. The resulting circuit is a |
| A. | SR flip-flop |
| B. | JK flip-flop |
| C. | D flip-flop |
| D. | T flip-flop |
| Answer» B. JK flip-flop | |
| 57. |
D flip-flop is used as |
| A. | Differentiator |
| B. | Divider circuit |
| C. | Delay switch |
| D. | All of these |
| Answer» D. All of these | |
| 58. |
Schmidt trigger is used as |
| A. | Voltage to frequency converter |
| B. | Frequency to voltage converter |
| C. | Square wave generator |
| D. | None of these |
| Answer» D. None of these | |
| 59. |
For a sinusoidal input, Schmidt trigger gives output as |
| A. | Sinusoidal |
| B. | Saw tooth wave |
| C. | Square wave |
| D. | None of these |
| Answer» D. None of these | |
| 60. |
Schmidt trigger can be used as |
| A. | Square wave generator |
| B. | Comparator |
| C. | Square wave generator and comparator |
| D. | None of these |
| Answer» D. None of these | |
| 61. |
Following flip-flop is used as latch |
| A. | JK flip-flop |
| B. | Master slave JK flip-flop |
| C. | T flip-flop |
| D. | SR flip-flop |
| Answer» E. | |
| 62. |
In a ripple counter using edge-triggered JK flip-flops, the pulse input is applied to |
| A. | Clock input of all flip-flops |
| B. | Clock input of one flip-flop |
| C. | J and K inputs of one flip-flop |
| D. | J and K inputs of all flip-flops |
| Answer» C. J and K inputs of one flip-flop | |
| 63. |
For the circuit shown below, Q = 0 initially. What shall be the subsequent states of Q when clock pulses are given? |
| A. | 1, 0, 1, 0, .......... |
| B. | 0, 0, 0, 0, .......... |
| C. | 1, 1, 1, 1, .......... |
| D. | 0, 1, 0, 1, .......... |
| Answer» B. 0, 0, 0, 0, .......... | |
| 64. |
The frequency of the clock signal applied to the rising edge triggered D flip-flop shown below is 10 kHz. What is the frequency of the signal available at Q? |
| A. | 2.5 kHz |
| B. | 5 kHz |
| C. | 10 kHz |
| D. | 20 kHz |
| Answer» C. 10 kHz | |
| 65. |
For the circuit shown below what is the frequency of the output Q? |
| A. | Twice the input clock frequency |
| B. | Half the input clock frequency |
| C. | Same as the input clock frequency |
| D. | Inverse of the propagation delay of the Flip-flop. |
| Answer» C. Same as the input clock frequency | |
| 66. |
For the circuit shown below, D has a transition from 0 to 1 after CLK changes from 1 to 0. Assume gate delays to be negligible Which of the following statements in true? |
| A. | Q goes to 1 at the CLK transition and stays at 1 |
| B. | Q goes to 0 at the CLK transition and stays at 0 |
| C. | Q goes to 1 at the CLK transition and goes to 0 when D goes to 1 |
| D. | Q goes to 0 at the CLK transition and goes to 1 when D goes to 1 |
| Answer» D. Q goes to 0 at the CLK transition and goes to 1 when D goes to 1 | |
| 67. |
A 1 s pulse can be converted into a 1 ms pulse by using |
| A. | A monostable multivibrator |
| B. | An astable multivibrator |
| C. | A bistable multivibrator |
| D. | JK flip-flops |
| Answer» B. An astable multivibrator | |
| 68. |
T flip-flop is used as |
| A. | Transfer data circuit |
| B. | Toggle switch |
| C. | Time delay switch |
| D. | None of these |
| Answer» C. Time delay switch | |
| 69. |
In a JK flip-flop the output Qn is '1'. It does not change when a clock pulse is applied. The possible combination of Jn and Kn could be (X denotes don't care) |
| A. | 'X' and '0' |
| B. | 'X' and '1' |
| C. | '0' and 'X' |
| D. | 'Y' and 'X' |
| Answer» B. 'X' and '1' | |
| 70. |
The race around condition exists in JK flip-flop if |
| A. | J = 0; K = 0 |
| B. | J = 1; K = 0 |
| C. | J = 0; K = 1 |
| D. | J = 1; K = 1 |
| Answer» E. | |
| 71. |
In T flip-flop the output frequency is |
| A. | Same as the input frequency |
| B. | Double of its input frequency |
| C. | One-half its input frequency |
| D. | None of these |
| Answer» C. One-half its input frequency | |
| 72. |
If the J-input of a J-K flip-flop is treated as input and an inverter is wired between J and K inputs, the J-K flip-flop becomes |
| A. | R-S flip-flop |
| B. | D flip-flop |
| C. | T flip-flop |
| D. | D latch |
| Answer» C. T flip-flop | |
| 73. |
The basic sequential logic building block in which the output follows the data input as long as the ENABLE input is active is |
| A. | J-K flip-flop |
| B. | D flip-flop |
| C. | T flip-flop |
| D. | D latch |
| Answer» E. | |
| 74. |
For one of the following conditions, clocked J-K flip-flop can be used as a divide-by-2 circuit when the input signal is applied at clock-input |
| A. | J = K = 1 and flip-flop has active-HIGH inputs |
| B. | J = K = 0 and flip-flop has active-HIGH inputs |
| C. | J = K = 1 and flip-flop active-Low inputs |
| D. | J = K = 1 and flip-flop should be a negative edge triggered. |
| Answer» B. J = K = 0 and flip-flop has active-HIGH inputs | |
| 75. |
In a R-S flip-flop with active-LOW inputs, for R = S = 0, Q output when the flip-flop is clocked is |
| A. | Indeterminate |
| B. | 0 |
| C. | 1 |
| D. | 1 if it was 0 and 0 if it was 1 |
| Answer» B. 0 | |
| 76. |
The advantage of serial transfer compared with parallel transfer for data transmission is that |
| A. | It needs only one wire |
| B. | It is faster |
| C. | BCD is compatible |
| D. | None of these |
| Answer» B. It is faster | |
| 77. |
Parallel operation is preferred because |
| A. | It is faster than serial operation |
| B. | It requires less memory |
| C. | Circuitry is simple |
| D. | None of these |
| Answer» B. It requires less memory | |
| 78. |
The two trip points in a Schmitt inverter are 1 5 V and 2.7 V. If the output is initially HIGH, it will go to LOW state when input voltage |
| A. | Exceeds 2.7 V |
| B. | Exceeds 1.5 V |
| C. | Is greater than 1.5 V and less than 2.7 V |
| D. | Is less than 1.5 V |
| Answer» B. Exceeds 1.5 V | |
| 79. |
The Q output in a presettable, clearable J-K flip-flop with active-LOW asynchronous inputs is logc 1 at a certain time. The output immediately after the flip-flop is clocked for J = 0, K = 1, Pr = 0, Cl = 1 will (Pr = Preset and Cr = Clear) |
| A. | Become 0 |
| B. | Toggle |
| C. | Remain 1 |
| D. | Become invalid |
| Answer» D. Become invalid | |
| 80. |
The maximum integer which can be stored on an 8-bit accumulator is |
| A. | 112 |
| B. | 200 |
| C. | 224 |
| D. | 255 |
| Answer» E. | |
| 81. |
The number of minimum clock cycles in a machine cycle for 8085 are |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 5 |
| Answer» D. 5 | |
| 82. |
The speed of a digital IC indicates |
| A. | How fast a flip-flop can change states |
| B. | How fast input triggers the output |
| C. | The rate at which output changes |
| D. | None of the above |
| Answer» B. How fast input triggers the output | |
| 83. |
With standard TTL, the fan-out equals |
| A. | 1 |
| B. | 2 |
| C. | 5 |
| D. | 10 |
| Answer» E. | |
| 84. |
The maximum number of TTL loads, a TTL device can drive is called the |
| A. | Index number |
| B. | Margin |
| C. | Fan-out |
| D. | Attenuation |
| Answer» D. Attenuation | |
| 85. |
Microprocessors can be |
| A. | Non-programmable |
| B. | Macro-programmable |
| C. | Micro-programmable |
| D. | Any of the above |
| Answer» E. | |
| 86. |
Floppy disc is a |
| A. | Fast storage |
| B. | Permanent storage |
| C. | Flexible storage |
| D. | All of the above |
| Answer» D. All of the above | |
| 87. |
A buffer is generally a.............input impedance and a...........output impedance. |
| A. | High, low |
| B. | Low, high |
| C. | Low, low |
| D. | High, high |
| Answer» B. Low, high | |
| 88. |
ROM memory represents |
| A. | Register open memory |
| B. | Read-only memory |
| C. | Read octave memory |
| D. | Record oscillation memory |
| Answer» C. Read octave memory | |
| 89. |
RAM memory represents |
| A. | Read-audio memory |
| B. | Radio-amplified memory |
| C. | Random-access memory |
| D. | Record-attenuated memory |
| Answer» D. Record-attenuated memory | |
| 90. |
A 4-bit counter with four flip-flops will count up to decimal |
| A. | 8 |
| B. | 15 |
| C. | 31 |
| D. | 63 |
| Answer» C. 31 | |
| 91. |
What will be the starting address of memory chip, given that memory address of last location of an 8K byte memory chip is FFFFH |
| A. | DEFFH |
| B. | E000H |
| C. | F000H |
| D. | None of these |
| Answer» C. F000H | |
| 92. |
Memory with highest storage capacity is |
| A. | Core memory |
| B. | Semiconductor memory |
| C. | Magnetic taps |
| D. | Magnetic disc |
| Answer» E. | |
| 93. |
Flip-flops are used for |
| A. | Counters |
| B. | Shift registers |
| C. | Transfer register |
| D. | All of the above |
| Answer» E. | |
| 94. |
The number of different Boolean functions of 4 variables is |
| A. | 216 |
| B. | 162 |
| C. | 42 |
| D. | 164 |
| Answer» B. 162 | |
| 95. |
Which one of the following is a volatile memory? |
| A. | Ferrite core |
| B. | Semiconductor RAM |
| C. | Semiconductor ROM |
| D. | None of these |
| Answer» E. | |
| 96. |
How many bits are stored by a 256 4 memory chip? |
| A. | 256 |
| B. | 512 |
| C. | 1024 |
| D. | 2048 |
| Answer» D. 2048 | |
| 97. |
First generation computers had maximum memory of |
| A. | 16 K |
| B. | 64 K |
| C. | 128 K |
| D. | 640 K |
| Answer» C. 128 K | |
| 98. |
The highest address in a 48 K memory expressed in decimal forms is |
| A. | 49,151 |
| B. | 24,131 |
| C. | 11,111 |
| D. | 6,450 |
| Answer» B. 24,131 | |
| 99. |
Semiconductor memories are |
| A. | Volatile and larger in size |
| B. | Volatile and smaller in size |
| C. | Non-volatile and larger in size |
| D. | Non-volatile and smaller in size |
| Answer» C. Non-volatile and larger in size | |
| 100. |
The programmable logic device (PLD) having a programmable AND-array at the input and a programmable OR-array at the output is called a |
| A. | Programmable logic array (PLA) |
| B. | Programmable array logic (PAL) |
| C. | Programmable gate array (PGA) |
| D. | Application-specific integrated circuit (ASIC) |
| Answer» B. Programmable array logic (PAL) | |