In a ripple counter using edge-triggered JK flip-flops, the pulse inpu – McqOptions

MCQOPTIONS

1.	In a ripple counter using edge-triggered JK flip-flops, the pulse input is applied to
A.	Clock input of all flip-flops
B.	Clock input of one flip-flop
C.	J and K inputs of one flip-flop
D.	J and K inputs of all flip-flops
Answer» C. J and K inputs of one flip-flop

Discussion

No Comment Found

Related MCQs

Consider the following statements: 1. A flip-flop is used to store 1-bit of information. 2. Race-around condition occurs in a JK flip-flop when both the inputs are 1. 3. Master-Slave configuration is used in flip-flops to store 2-bits of information. 4. A transparent latch consists of a D-type flip-flop. Which of the above statements is/are correct?
For each of the positive edge-triggered JK flip-flop used in the following figure, the propagation delay is T.Which of the following waveforms correctly represents the output at Q1?
Consider the following statements: For a Master-Slave JK flip-flop, 1. the toggle frequency is the maximum clock frequency at which the flip-flop will toggle reliably. 2. the data input must preceds the clock triggering edge transition time by some minimum time. 3. the data input must remain fixed for a given time after, the clock triggering edge transition time for reliable operation. 4. propagation delay time is equal to the rise time and fall time of the data. Which of the above statements is/are correct?
In a JK flip-flop we have J = Q and K = 1 (shown in figure). Assuming the flip-flop was initially cleaned and then clocked for 6-pulses, the sequence at the Q will be
The architecture of a PLA device differs from that of a PROM device in the following
A Schmitt trigger
Simplify (X + Y) (X + Y)
The Boolean expression A + B + C is
Which one of the following is not a valid rule of Boolean algebra?
The Boolean expression A BC D is