MCQOPTIONS
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MCQOPTIONS
This section includes 289 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Electronics knowledge and support exam preparation. Choose a topic below to get started.
| 251. |
How many flip-flops are needed for MOD-16 ring counter and MOD-16 Johnson counter? |
| A. | 16, 16 |
| B. | 16, 8 |
| C. | 4, 8 |
| D. | 8, 16 |
| Answer» C. 4, 8 | |
| 252. |
For the ring oscillator shown the propagation delay of each inverter is 125 pico sec. What is the fundamental frequency of oscillator output? |
| A. | 10 MHz |
| B. | 100 MHz |
| C. | 1 GHz |
| D. | |
| E. | 2 GHz |
| Answer» E. 2 GHz | |
| 253. |
A 0 to 6 count consists of 3 flip-flops and a combination circuit of 2 input gate. The combination consists of |
| A. | One AND gate |
| B. | One OR gate |
| C. | One AND gate and one OR gate |
| D. | Two AND gates |
| Answer» B. One OR gate | |
| 254. |
A 4-bit binary ripple counter uses flip-flops with a propagation delay time of 25 ns each. The maximum possible time required for change of the state will be |
| A. | 25 ns |
| B. | 50 ns |
| C. | 75 ns |
| D. | 100 ns |
| Answer» E. | |
| 255. |
A divide by 72 counter can be realized by using |
| A. | 6 number of MOD-12 counter |
| B. | 12 number of MOD-6 counter |
| C. | One MOD-12 counter followed by one MOD-6 counter |
| D. | All of these |
| Answer» D. All of these | |
| 256. |
A 4-bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each flip-flop is 50 ns, the maximum clock frequency is equal to |
| A. | 2 MHz |
| B. | 3 MHz |
| C. | 4 MHz |
| D. | 5 MHz |
| Answer» E. | |
| 257. |
A ring counter consist of five flip-flops will have |
| A. | 5 states |
| B. | 10 states |
| C. | 32 states |
| D. | None of these |
| Answer» B. 10 states | |
| 258. |
The number of unused states in a 4-bit Johnson counter is |
| A. | 2 |
| B. | 4 |
| C. | 8 |
| D. | 12 |
| Answer» D. 12 | |
| 259. |
Minimum number of JK flip-flops are needed to construct a BCD counter is |
| A. | 2 |
| B. | 4 |
| C. | 8 |
| D. | 6 |
| Answer» C. 8 | |
| 260. |
The minimum number of flip-flops required to construct a MOD-64 (divide by 64) ripple counter, are |
| A. | 4 flip-flops |
| B. | 6 flip-flops |
| C. | 16 flip-flops |
| D. | 64 flip-flops |
| Answer» C. 16 flip-flops | |
| 261. |
The maximum frequency at which a MOD-16 ripple counter using four JK flip-flops with propagation delay time of 50 ns is |
| A. | 4 MHz |
| B. | 5 MHz |
| C. | 3.2 MHz |
| D. | 320 MHz |
| Answer» C. 3.2 MHz | |
| 262. |
The type of register, in which data is entered into it only one bit at a time, but has all data bits available as output, is |
| A. | Serial in/parallel out register |
| B. | Serial in/serial out register |
| C. | Parallel in/serial out register |
| D. | Parallel in/parallel out register. |
| Answer» B. Serial in/serial out register | |
| 263. |
The type of register, in which we have access only to left most and right most flip-flops is |
| A. | Shift left and shift right registers |
| B. | Serial in/serial out register |
| C. | Parallel in/serial out register |
| D. | Serial in/parallel out register |
| Answer» C. Parallel in/serial out register | |
| 264. |
The counter which requires maximum number of flip-flop for a given MOD number is |
| A. | Ripple counter |
| B. | BCD counter |
| C. | Ring counter |
| D. | Programmable counter |
| Answer» D. Programmable counter | |
| 265. |
The table which shows the necessary levels at J and K inputs to produce every possible flip-flop state transition is called |
| A. | Truth table of JK flip-flop |
| B. | Excitation table of JK flip-flop |
| C. | Excitation table of MOD-N counter using JK flip-flop |
| D. | None of these |
| Answer» C. Excitation table of MOD-N counter using JK flip-flop | |
| 266. |
The output frequency of a MOD-16 counter, checked from a 10 kHz clock input signal is |
| A. | 10 kHz |
| B. | 26 kHz |
| C. | 160 kHz |
| D. | 625 kHz |
| Answer» D. 625 kHz | |
| 267. |
The output frequency of a decode counter, which is clocked from a 50 kHz signal is |
| A. | 5 kHz |
| B. | 50 kHz |
| C. | 500 kHz |
| D. | 5000 kHz |
| Answer» B. 50 kHz | |
| 268. |
ABCD counter has |
| A. | 3 distinct states |
| B. | 8 distinct states |
| C. | 10 distinct states |
| D. | 16 distinct states |
| Answer» D. 16 distinct states | |
| 269. |
The number of flip-flops required for a MOD-16 ring counter are |
| A. | 4 flip-flops |
| B. | 8 flip-flops |
| C. | 10 flip-flops |
| D. | 16 flip-flops |
| Answer» E. | |
| 270. |
A MOD-5 synchronous counter is desigend using JK flipflops. The number of counts skipped by it will be |
| A. | 2 |
| B. | 3 |
| C. | 5 |
| D. | 0 |
| Answer» C. 5 | |
| 271. |
The maximum modulo number that can be obtained by a ripple counter using five flip-flops is |
| A. | 16 |
| B. | 32 |
| C. | 5 |
| D. | 31 |
| Answer» C. 5 | |
| 272. |
The minimum number of flip-flop required for a MOD-10 ripple counter are |
| A. | 4 |
| B. | 2 |
| C. | 10 |
| D. | 5 |
| Answer» B. 2 | |
| 273. |
The black box in the figure consists of a minimum complexity circuit that uses only AND, OR and NOT gates. The function f(x, y, z) = 1 whenever x, y are different and 0 otherwise. In addition the 3 inputs x, y, z are never all the same value. Which one of the following equations leads to the correct design for the minimum complexity circuit? |
| A. | x' y + xy' |
| B. | x + y'z |
| C. | x'y'z' + xy'z |
| D. | xy + y'z + z' |
| Answer» B. x + y'z | |
| 274. |
The Boolean functions can be expressed in canonical SOP (sum of products) and POS (product of sums) form. For the functions, Y = A + |
| A. | Y = (1, 2, 6, 7) and Y = (0, 2, 4) |
| B. | Y = (1, 4, 5, 6, 7) and Y = (0, 2, 3) |
| C. | Y = (1, 2, 5, 6, 7) and Y = (0, 1, 3) |
| D. | Y = (1, 2, 4, 5, 6, 7) and Y= (0, 2, 3, 4) |
| Answer» C. Y = (1, 2, 5, 6, 7) and Y = (0, 1, 3) | |
| 275. |
A full-adder can be made out of |
| A. | Two half-adders |
| B. | Two half-adders and a NOT gate |
| C. | Two half-adders and an OR gate |
| D. | Two half-adders and an AND gate |
| Answer» D. Two half-adders and an AND gate | |
| 276. |
Consider the following statements: A multiplexer |
| A. | 1, 2 and 4 |
| B. | 2, 3 and 4 |
| C. | 1, 3 and 4 |
| D. | 1, 2 and 3 Answers with Explanatory |
| Answer» D. 1, 2 and 3 Answers with Explanatory | |
| 277. |
Which of the following is known as half-adder? |
| A. | XOR gate |
| B. | XNOR gate |
| C. | NAND gate |
| D. | NOR gate |
| Answer» B. XNOR gate | |
| 278. |
To add two m-bit numbers, the required number of half adder is |
| A. | 2m 1 |
| B. | 2m 1 |
| C. | 2m + 1 |
| D. | 2m |
| Answer» B. 2m 1 | |
| 279. |
The difference bit output of a half- |
| A. | subtractor is the same as |
| B. | Difference bit output of a full-subtractor |
| C. | Sum bit output of a half-adder |
| D. | Sum bit output of full-adder |
| E. | Carry bit output of a half-adder |
| Answer» C. Sum bit output of a half-adder | |
| 280. |
Which of the following statement is not correct? Conversion of Excess-3 code to BCD can be achieved by using |
| A. | Discretic gate |
| B. | 4: 16 demultiplexer |
| C. | A four-bit full adder |
| D. | A four-bit half adder |
| Answer» E. | |
| 281. |
How many inputs and outputs does a full-adder have |
| A. | Two inputs, two outputs |
| B. | Two inputs, one output |
| C. | Three inputs, two outputs |
| D. | Two inputs, three outputs |
| Answer» D. Two inputs, three outputs | |
| 282. |
The logic network shown below is |
| A. | Half adder |
| B. | Half subtractor |
| C. | Full adder |
| D. | Full subtractor |
| Answer» D. Full subtractor | |
| 283. |
A full adder can be realized by using |
| A. | One half-adder, two OR gates |
| B. | Two half-adders, one OR gate |
| C. | Two half adders, two OR gates |
| D. | None of these |
| Answer» C. Two half adders, two OR gates | |
| 284. |
How many inputs and outputs does a full subtractor circuit have |
| A. | Two inputs, one output |
| B. | Two inputs, two outputs |
| C. | Two inputs, three outputs |
| D. | Three inputs, two outputs |
| Answer» E. | |
| 285. |
In addition of two binary variables A and B results into a SUM and a CARRY output. Consider the following expressions for the SUM and CARRY outputs. |
| A. | 1 and 2 |
| B. | 2 and 3 |
| C. | 2 and 4 |
| D. | 1 and 4 |
| Answer» C. 2 and 4 | |
| 286. |
A 4 1 MUX is used to implement a 3-input Boolean function as shown in figure. The Boolean function F (A, B, C) implement is A B A 1 F(A, B, C) |
| A. | F (A, B, C) = (1, 2, 4, 6) |
| B. | F (A, B, C) = (1, 2, 6) |
| C. | F (A, B, C) = (2, 4, 5, 6) |
| D. | F (A, B, C) = (1, 5, 6) |
| Answer» B. F (A, B, C) = (1, 2, 6) | |
| 287. |
Which of the following circuits come under the class of combinational logic circuits: |
| A. | 1 only |
| B. | 3 and 4 |
| C. | 4 and 5 |
| D. | 1, 2 and 3 |
| Answer» E. | |
| 288. |
A digital multiplexer can be used for which of the following? |
| A. | 1, 3 and 4 |
| B. | 2, 3 and 4 |
| C. | 1 and 2 only |
| D. | 2 and 3 only |
| Answer» D. 2 and 3 only | |
| 289. |
It is required to construct a 2n to 1 multiplexer by using 2 to 1 multiplexers only. How many of 2 to 1 multiplexers are needed? |
| A. | n |
| B. | 22n |
| C. | 2n 1 |
| D. | 2n+1 |
| Answer» B. 22n | |