The problem of the V of a TTL IC being too low to drive a CMOS circuit and meet the CMOS requirement of V is usually easily overcome by:

adding a fixed voltage-divider bias resistive network at the output of the TTL device

avoiding this condition and only using TTL to drive TTL

adding an external pull-down resistor to ground

adding an external pull-up resistor to

Why are the maximum value of and the minimum value of used to determine the noise margin rather than the typical values for these parameters?

These are worst-case conditions.

These are best-case conditions.

It doesn't matter what values are used.

How is the speed–power product of a logic family determined?

The propagation delay in ns is multiplied by the power dissipation in W.

The propagation delay in s is multiplied by the power dissipation in mW.

The propagation delay in ms is multiplied by the power dissipation in W.

The propagation delay in ns is multiplied by the power dissipation in mW.

The propagation delay in ns is multiplied by the power dissipation in W.

As a general rule, the lower the value of the speed–power product, the better the device because of its:

long propagation delay and high power consumption

long propagation delay and low power consumption

How can ECL have both a NOR and an OR output?

ECL does not have this feature.

They are simply the inverse of each other.

PMOS and NMOS ________.

are enhancement-type CMOS devices used to produce a series of high-speed logic known as 74HC

represent MOSFET devices utilizing either P-channel or N-channel devices exclusively within a given gate

are enhancement-type CMOS devices used to produce a series of high-speed logic known as 74HC

represent positive and negative MOS-type devices, which can be operated from differential power supplies and are compatible with operational amplifiers

The problem of the VOH(min) of a TTL IC being too low to drive a CMOS circuit and meet the CMOS requirement of VIH(min) is usually easily overcome by:

adding a fixed voltage-divider bias resistive network at the output of the TTL device

avoiding this condition and only using TTL to drive TTL

adding an external pull-down resistor to ground

adding an external pull-up resistor to VCC

Why is a pull-up resistor needed when connecting TTL logic to CMOS logic?

to decrease the output HIGH voltage

to increase the output LOW voltage

to decrease the output LOW voltage

to increase the output HIGH voltage

to decrease the output HIGH voltage

As a general rule, the lower the value of the speed‚Äìpower product, the better the device because of its:

long propagation delay and high power consumption

long propagation delay and low power consumption

When is a level-shifter circuit needed in interfacing logic?

A level shifter is always needed.

A level shifter is never needed.

when the supply voltages are the same

when the supply voltages are different

What is the major advantage of ECL logic?

wide range of operating voltage

Why is a decoupling capacitor needed for TTL ICs and where should it be connected?

to block dc, connect to input pins

to reduce noise, connect to input pins

to reduce the effects of noise, connect between power supply and ground

Why are the maximum value of VOL and the minimum value of VOH used to determine the noise margin rather than the typical values for these parameters?

These are worst-case conditions.

These are best-case conditions.

It doesn't matter what values are used.

Why is the operating frequency for CMOS devices critical for determining power dissipation?

At high frequencies, the gate will only be able to deliver 70.7 % of rated power and charging and discharging the gate capacitance will draw a heavy current from the power supply and thus increase power dissipation.

At low frequencies, power dissipation increases.

At high frequencies, the gate will only be able to deliver 70.7 % of rated power.

At high frequencies, charging and discharging the gate capacitance will draw a heavy current from the power supply and thus increase power dissipation.

At high frequencies, the gate will only be able to deliver 70.7 % of rated power and charging and discharging the gate capacitance will draw a heavy current from the power supply and thus increase power dissipation.

The word "interfacing" as applied to digital electronics usually means:

any gate that is a TTL operational amplifier designed to condition signals between NMOS transistors

a conditioning circuit connected between a standard TTL NAND gate and a standard TTL OR gate

a circuit connected between the driver and load to condition a signal so that it is compatible with the load

any gate that is a TTL operational amplifier designed to condition signals between NMOS transistors

any TTL circuit that is an input buffer stage

From the following specifications determine the fan-out for the logic family.

HIGH state is 4, LOW state is 8

HIGH state is 16, LOW state is 8

HIGH state is 8, LOW state is 16

HIGH state is 4, LOW state is 8

HIGH state is 8, LOW state is 4

How is the speed‚Äìpower product of a logic family determined?

The propagation delay in ns is multiplied by the power dissipation in W.

The propagation delay in s is multiplied by the power dissipation in mW.

The propagation delay in ms is multiplied by the power dissipation in W.

The propagation delay in ns is multiplied by the power dissipation in mW.

The propagation delay in ns is multiplied by the power dissipation in W.

The high input impedance of MOSFETs:

reduces input current and power dissipation

The problem of different current requirements when CMOS logic circuits are driving TTL logic circuits can usually be overcome by the addition of:

a CMOS inverting bilateral switch between the stages

a TTL tristate inverting buffer between the stages

a CMOS noninverting bilateral switch between the stages

a CMOS buffer or inverting buffer

What is the difference between the 74HC00 series and the 74HCT00 series of CMOS logic?

The HCT series is not input and output voltage compatible with TTL.

The HCT series is input and output voltage compatible with TTL.

The HCT series is not input and output voltage compatible with TTL.

The term buffer/driver signifies the ability to provide low output currents to drive light loads.

represent MOSFET devices utilizing either P-channel or N-channel devices exclusively within a given gate

are enhancement-type CMOS devices used to produce a series of high-speed logic known as 74HC

64 + Mcqs in Logic Families And Their Characteristics Page 1 McqOptions

1.	Assume that a particular IC has a supply voltage () equal to +5 V and = 10 mA and = 23 mA. What is the power dissipation for the chip?
A.	50 mW
B.	82.5 mW
C.	115 mW
D.	165 mW
Answer» C. 115 mW

3.	Why are the maximum value of and the minimum value of used to determine the noise margin rather than the typical values for these parameters?
A.	These are worst-case conditions.
B.	These are normal conditions.
C.	These are best-case conditions.
D.	It doesn't matter what values are used.
Answer» B. These are normal conditions.

4.	The rise time () is the time it takes for a pulse to rise from its ________ point up to its ________ point. The fall time () is the length of time it takes to fall from the ________ to the ________ point.
A.	10%, 90%, 90%, 10%
B.	90%, 10%, 10%, 90%
C.	20%, 80%, 80%, 20%
D.	10%, 70.7%, 70.7%, 10%
Answer» B. 90%, 10%, 10%, 90%

5.	The problem of interfacing IC logic families that have different supply voltages ('s) can be solved by using a:
A.	level-shifter
B.	tristate shifter
C.	decoupling capacitor
D.	pull-down resistor
Answer» B. tristate shifter

8.	Interfacing (74HCMOS to 74ALSTTl or 74TTL to 74LSTTL) can be done with no danger.
A.	1
B.
Answer» C.

9.	Schottky logic overcomes the saturation and stored charge problem by placing a Schottky diode across the base-to-collector junction.
A.	1
B.
Answer» B.

10.	PMOS and NMOS are commonly used for small memories and microprocessors.
A.	1
B.
Answer» C.

11.	A pulse is not perfectly square; it takes time for the digital level to rise from 0 up to 1 and to fall from 1 down to 0.
A.	1
B.
Answer» B.

14.	In TTL the noise margin is between 0.8 V and 0.4 V.
A.	1
B.
Answer» B.

15.	The rise time (tr) is the time it takes for a pulse to rise from its ________ point up to its ________ point. The fall time (tf) is the length of time it takes to fall from the ________ to the ________ point.
A.	10%, 90%, 90%, 10%
B.	90%, 10%, 10%, 90%
C.	20%, 80%, 80%, 20%
D.	10%, 70.7%, 70.7%, 10%
Answer» B. 90%, 10%, 10%, 90%

17.	Using the schematic diagram of a TTL NAND gate, determine the state of each transistor (ON or OFF) when all inputs are high.
A.	Q1-ON, Q2-OFF, Q3-ON, Q4-OFF
B.	Q1-ON, Q2-ON, Q3-OFF, Q4-OFF
C.	Q1-OFF, Q2-OFF, Q3-ON, Q4-ON
D.	Q1-OFF, Q2-ON, Q3-OFF, Q4-ON
Answer» E.

21.	What is the range of invalid TTL output voltage?
A.	0.0‚Äì0.4 V
B.	0.4‚Äì2.4 V
C.	2.4‚Äì5.0 V
D.	0.0‚Äì5.0 V
Answer» C. 2.4‚Äì5.0 V

29.	Can a 74HCMOS logic gate directly connect to a 74ALSTTL gate?
A.	Yes
B.	No
Answer» B. No

30.	Fan-out is determined by taking the ________ result(s) of ________.
A.	smaller,
B.	larger,
C.	smaller,
D.	average,
Answer» D. average,

32.	What should be done with unused inputs to a TTL NAND gate?
A.	let them float
B.	tie them LOW
C.	tie them HIGH
Answer» D.

22.	What is the major advantage of ECL logic?
A.	very high speed
B.	wide range of operating voltage
C.	very low cost
D.	very high power
Answer» B. wide range of operating voltage

28.	The output current capability of a single 7400 NAND gate when HIGH is called ________.
A.	source current
B.	sink current
C.	IOH
D.	source current of IOH
Answer» B. sink current

31.	The basic part numbers of ICs are the same regardless of the manufacturer because digital logic ICs have been standardized.
A.	1
B.
C.	1
D.
Answer» B.

33.	The AND is the simplest of the gates, requiring the least amount of circuitry to implement in TTL.
A.	1
B.
Answer» C.

34.	The most common TTL series ICs are:
A.	E-MOSFET
B.	7400
C.	quad
D.	AC00
Answer» C. quad

35.	Propagation delay in TTL is due to slow switching speeds.
A.	1
B.
Answer» C.

36.	An open collector output can ________ current, but it cannot ________.
A.	sink, source current
B.	source, sink current
C.	sink, source voltage
D.	source, sink voltage
Answer» B. source, sink current

38.	Ten TTL loads per TTL driver is known as:
A.	noise immunity
B.	fan-out
C.	power dissipation
D.	propagation delay
Answer» C. power dissipation

39.	The TTL HIGH level source current is higher than the LOW level sinking current.
A.	1
B.
Answer» C.

40.	Why is a pull-up resistor needed for an open collector gate?
A.	to provide Vcc for the IC
B.	to provide ground for the IC
C.	to provide the HIGH voltage
D.	to provide the LOW voltage
Answer» D. to provide the LOW voltage

Explore topic-wise MCQs in Digital Electronics.

Assume that a particular IC has a supply voltage () equal to +5 V and = 10 mA and = 23 mA. What is the power dissipation for the chip?

The problem of the V of a TTL IC being too low to drive a CMOS circuit and meet the CMOS requirement of V is usually easily overcome by:

Why are the maximum value of and the minimum value of used to determine the noise margin rather than the typical values for these parameters?

The rise time () is the time it takes for a pulse to rise from its ________ point up to its ________ point. The fall time () is the length of time it takes to fall from the ________ to the ________ point.

The problem of interfacing IC logic families that have different supply voltages ('s) can be solved by using a:

How is the speed–power product of a logic family determined?

As a general rule, the lower the value of the speed–power product, the better the device because of its:

Interfacing (74HCMOS to 74ALSTTl or 74TTL to 74LSTTL) can be done with no danger.

Schottky logic overcomes the saturation and stored charge problem by placing a Schottky diode across the base-to-collector junction.

PMOS and NMOS are commonly used for small memories and microprocessors.

A pulse is not perfectly square; it takes time for the digital level to rise from 0 up to 1 and to fall from 1 down to 0.

How can ECL have both a NOR and an OR output?

PMOS and NMOS ________.

In TTL the noise margin is between 0.8 V and 0.4 V.

The rise time (tr) is the time it takes for a pulse to rise from its ________ point up to its ________ point. The fall time (tf) is the length of time it takes to fall from the ________ to the ________ point.

The problem of the VOH(min) of a TTL IC being too low to drive a CMOS circuit and meet the CMOS requirement of VIH(min) is usually easily overcome by:

Using the schematic diagram of a TTL NAND gate, determine the state of each transistor (ON or OFF) when all inputs are high.

Why is a pull-up resistor needed when connecting TTL logic to CMOS logic?

As a general rule, the lower the value of the speed‚Äìpower product, the better the device because of its:

When is a level-shifter circuit needed in interfacing logic?

What is the range of invalid TTL output voltage?

What is the major advantage of ECL logic?

Why is a decoupling capacitor needed for TTL ICs and where should it be connected?

A typical fan-out for most TTL is 9.

Why are the maximum value of VOL and the minimum value of VOH used to determine the noise margin rather than the typical values for these parameters?

Why is the operating frequency for CMOS devices critical for determining power dissipation?

The problem of interfacing IC logic families that have different supply voltages (VCC's) can be solved by using a:

The output current capability of a single 7400 NAND gate when HIGH is called ________.

Can a 74HCMOS logic gate directly connect to a 74ALSTTL gate?

Fan-out is determined by taking the ________ result(s) of ________.

The basic part numbers of ICs are the same regardless of the manufacturer because digital logic ICs have been standardized.

What should be done with unused inputs to a TTL NAND gate?

The AND is the simplest of the gates, requiring the least amount of circuitry to implement in TTL.

The most common TTL series ICs are:

Propagation delay in TTL is due to slow switching speeds.

An open collector output can ________ current, but it cannot ________.

The word "interfacing" as applied to digital electronics usually means:

Ten TTL loads per TTL driver is known as:

The TTL HIGH level source current is higher than the LOW level sinking current.

Why is a pull-up resistor needed for an open collector gate?

From the following specifications determine the fan-out for the logic family.

How is the speed‚Äìpower product of a logic family determined?

The high input impedance of MOSFETs:

The time needed for an output to change from the result of an input change is known as:

The problem of different current requirements when CMOS logic circuits are driving TTL logic circuits can usually be overcome by the addition of:

If all inputs to a TTL NAND gate are low, what is the ON, OFF condition of each transistor in the circuit?

What is the difference between the 74HC00 series and the 74HCT00 series of CMOS logic?

Which logic family is characterized by a multiemitter transistor on the input?

How many 74LSTTL logic gates can be driven from a 74TTL gate?

The term buffer/driver signifies the ability to provide low output currents to drive light loads.

The rise time () is the time it takes for a pulse to rise from its point up to its point. The fall time () is the length of time it takes to fall from the to the point.

The rise time (tr) is the time it takes for a pulse to rise from its point up to its point. The fall time (tf) is the length of time it takes to fall from the to the point.

Fan-out is determined by taking the result(s) of .

An open collector output can current, but it cannot .

43.	The high input impedance of MOSFETs:
A.	allows faster switching
B.	reduces input current and power dissipation
C.	prevents dense packing
D.	creates low-noise reactions
Answer» C. prevents dense packing

47.	What is the difference between the 74HC00 series and the 74HCT00 series of CMOS logic?
A.	The HCT series is faster.
B.	The HCT series is slower.
C.	The HCT series is input and output voltage compatible with TTL.
D.	The HCT series is not input and output voltage compatible with TTL.
Answer» D. The HCT series is not input and output voltage compatible with TTL.

48.	Which logic family is characterized by a multiemitter transistor on the input?
A.	ECL
B.	CMOS
C.	TTL
D.	None of the above
Answer» D. None of the above

49.	How many 74LSTTL logic gates can be driven from a 74TTL gate?
A.	10
B.	20
C.	200
D.	400
Answer» C. 200