MCQOPTIONS
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MCQOPTIONS
This section includes 51 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Electronics knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Implementation of the Boolean expression results in ________. |
| A. | three AND gates, one OR gate |
| B. | three AND gates, one NOT gate, one OR gate |
| C. | three AND gates, one NOT gate, three OR gates |
| D. | three AND gates, three OR gates |
| Answer» C. three AND gates, one NOT gate, three OR gates | |
| 2. |
Before an SOP implementation, the expression would require a total of how many gates? |
| A. | 1 |
| B. | 2 |
| C. | 4 |
| D. | 5 |
| Answer» E. | |
| 3. |
Assume you have A, B, C, and D available but not their complements. The minimum number of 2-input NAND gates required to implement the equation is ________. |
| A. | 3 |
| B. | 4 |
| C. | 5 |
| D. | 6 |
| Answer» D. 6 | |
| 4. |
How many AND gates are required to implement the Boolean expression, ? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» D. 4 | |
| 5. |
How many NOT gates are required to implement the Boolean expression, ? |
| A. | 1 |
| B. | 2 |
| C. | 4 |
| D. | 5 |
| Answer» C. 4 | |
| 6. |
A is defined as ________. |
| A. | a common point in a circuit |
| B. | a circuit implemented as a sum-of-products |
| C. | the output signals from a circuit |
| D. | a shorted input |
| Answer» B. a circuit implemented as a sum-of-products | |
| 7. |
The expression can be directly implemented using only ________. |
| A. | an XOR gate |
| B. | an XNOR gate |
| C. | an AOI circuit |
| D. | three 2-input NAND gates |
| Answer» B. an XNOR gate | |
| 8. |
To implement the expression , it takes one OR gate and ________. |
| A. | three AND gates and three inverters |
| B. | three AND gates and four inverters |
| C. | three AND gates |
| D. | one AND gate |
| Answer» B. three AND gates and four inverters | |
| 9. |
A logic circuit with an output consists of ________. |
| A. | two AND gates, two OR gates, two inverters |
| B. | three AND gates, two OR gates, one inverter |
| C. | two AND gates, one OR gate, two inverters |
| D. | two AND gates, one OR gate |
| Answer» D. two AND gates, one OR gate | |
| 10. |
Referring to the GAL diagram, which is the correct logic function? |
| A. | [A]. |
| B. | [B]. |
| C. | [C]. |
| D. | [D]. |
| Answer» B. [B]. | |
| 11. |
One positive pulse with tw = 75 µs is applied to one of the inputs of an exclusive-OR circuit. A second positive pulse with tw = 15 µs is applied to the other input beginning 20 µs after the leading edge of the first pulse. Which statement describes the output in relation to the inputs? |
| A. | The exclusive-OR output is a 20 s pulse followed by a 40 s pulse, with a separation of 15 s between the pulses. |
| B. | The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, with a separation of 40 s between the pulses. |
| C. | The exclusive-OR output is a 15 s pulse followed by a 40 s pulse. |
| D. | *The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, followed by a 40 s pulse. |
| Answer» E. | |
| 12. |
One possible output expression for an AND-OR-Invert circuit having one AND gate with inputs A, B, and C and one AND gate with inputs D and E is ________. |
| A. | [A]. |
| B. | [B]. |
| C. | [C]. |
| D. | [D]. |
| Answer» D. [D]. | |
| 13. |
The Boolean SOP expression obtained from the truth table below is ________. |
| A. | [A]. |
| B. | [B]. |
| C. | [C]. |
| D. | None of these |
| Answer» D. None of these | |
| 14. |
The 8-input XOR circuit shown has an output of Y = 1. Which input combination below (ordered A – H) is correct? |
| A. | 10111100 |
| B. | 10111000 |
| C. | 11100111 |
| D. | 00011101 |
| Answer» B. 10111000 | |
| 15. |
A 4-variable AND-OR-Invert circuit produces a 0 at its Y output. Which combination of inputs is correct? |
| A. | [A]. |
| B. | [B]. |
| C. | [C]. |
| D. | none of the above |
| Answer» D. none of the above | |
| 16. |
A node is defined as ________. |
| A. | a common point in a circuit |
| B. | a circuit implemented as a sum-of-products |
| C. | the output signals from a circuit |
| D. | a shorted input |
| Answer» B. a circuit implemented as a sum-of-products | |
| 17. |
The output of an AND gate is HIGH when any input is HIGH. |
| A. | 1 |
| B. | |
| Answer» C. | |
| 18. |
Assume that you have a 3-input NAND gate but need only a 2-input gate. The unused input should be ________. |
| A. | connected to ground |
| B. | left open |
| C. | connected to a HIGH |
| D. | any of the above |
| Answer» D. any of the above | |
| 19. |
Using the universal property of a NAND gate, one or more NAND gates can be used to replace an ________. |
| A. | OR gate |
| B. | AND gate |
| C. | inverter |
| D. | any of the above |
| Answer» E. | |
| 20. |
An exclusive-OR gate's output is HIGH when its inputs are equal. |
| A. | 1 |
| B. | |
| Answer» C. | |
| 21. |
A NOR gate's truth table is the opposite of that of an OR gate. |
| A. | 1 |
| B. | |
| Answer» B. | |
| 22. |
A VHDL component is a predefined logic function. |
| A. | 1 |
| B. | |
| Answer» C. | |
| 23. |
The inverter can be produced with how many NAND gates? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» B. 2 | |
| 24. |
The symbol shown represents a(n) ________. |
| A. | AND gate |
| B. | OR gate |
| C. | NAND gate |
| D. | NOR gate |
| Answer» E. | |
| 25. |
When the output of an AND-OR circuit is complemented, it results in an AND-OR-Invert circuit. |
| A. | 1 |
| B. | |
| Answer» B. | |
| 26. |
The expression can be directly implemented using only ________. |
| A. | an XOR gate |
| B. | an XNOR gate |
| C. | an AOI circuit |
| D. | three 2-input NAND gates |
| Answer» D. three 2-input NAND gates | |
| 27. |
A NAND gate can function as a negative-OR gate. |
| A. | 1 |
| B. | |
| Answer» B. | |
| 28. |
If both inputs of a 2-input NOR gate are connected, the gate will function as an ________. |
| A. | OR gate |
| B. | AND gate |
| C. | inverter |
| D. | any of the above |
| Answer» D. any of the above | |
| 29. |
How many NOT gates are required to implement the Boolean expression, ? |
| A. | 1 |
| B. | 2 |
| C. | 4 |
| D. | 5 |
| Answer» C. 4 | |
| 30. |
The symbol shown represents ________. |
| A. | AND-OR logic |
| B. | AOI logic |
| C. | XOR gate |
| D. | XNOR gate |
| Answer» B. AOI logic | |
| 31. |
A 4-variable AND-OR circuit produces a 1 at its Y output. Which combination of inputs is correct? |
| A. | A = 0, B = 0, C = 0, D = 0 |
| B. | A = 0, B = 1, C = 1, D = 0 |
| C. | A = 1, B = 1, C = 0, D = 0 |
| D. | A = 1, B = 0, C = 0, D = 0 |
| Answer» D. A = 1, B = 0, C = 0, D = 0 | |
| 32. |
Implementing the expression using NAND logic, we get: |
| A. | (A) |
| B. | (B) |
| C. | (C) |
| D. | (D) |
| Answer» C. (C) | |
| 33. |
If one input to a 2-input AND gate is HIGH, the output reflects the other input. |
| A. | 1 |
| B. | |
| Answer» B. | |
| 34. |
An AND gate is a universal gate. |
| A. | 1 |
| B. | |
| Answer» C. | |
| 35. |
A NOR gate is a universal gate. |
| A. | 1 |
| B. | |
| C. | 1 |
| D. | |
| Answer» B. | |
| 36. |
A logic circuit with an output consists of ________. |
| A. | two AND gates, two OR gates, two inverters |
| B. | three AND gates, two OR gates, one inverter |
| C. | two AND gates, one OR gate, two inverters |
| D. | two AND gates, one OR gate |
| Answer» D. two AND gates, one OR gate | |
| 37. |
The following waveform pattern is for a(n) ________. |
| A. | 2-input AND gate |
| B. | 2-input OR gate |
| C. | Exclusive-OR gate |
| D. | None of the above |
| Answer» C. Exclusive-OR gate | |
| 38. |
One positive pulse with tw = 75 µs is applied to one of the inputs of an exclusive-OR circuit. A second positive pulse with tw = 15 µs is applied to the other input beginning 20 µs after the leading edge of the first pulse. Which statement describes the output in relation to the inputs? |
| A. | The exclusive-OR output is a 20 s pulse followed by a 40 s pulse, with a separation of 15 s between the pulses. |
| B. | The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, with a separation of 40 s between the pulses. |
| C. | The exclusive-OR output is a 15 s pulse followed by a 40 s pulse. |
| D. | *The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, followed by a 40 s pulse. |
| Answer» E. | |
| 39. |
How many AND gates are required to implement the Boolean expression, ? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» D. 4 | |
| 40. |
How many 2-input NOR gates does it take to produce a 2-input NAND gate? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» E. | |
| 41. |
Implementing the expression with NOR logic, we get: |
| A. | (A) |
| B. | (B) |
| C. | (C) |
| D. | (D) |
| Answer» B. (B) | |
| 42. |
A gate can drive a number of load gate inputs up to its specified ________. |
| A. | supply voltage |
| B. | noise margin |
| C. | fan-in |
| D. | fan-out |
| Answer» E. | |
| 43. |
Before an SOP implementation, the expression would require a total of how many gates? |
| A. | 1 |
| B. | 2 |
| C. | 4 |
| D. | 5 |
| Answer» E. | |
| 44. |
Implementation of the Boolean expression results in ________. |
| A. | three AND gates, one OR gate |
| B. | three AND gates, one NOT gate, one OR gate |
| C. | three AND gates, one NOT gate, three OR gates |
| D. | three AND gates, three OR gates |
| Answer» C. three AND gates, one NOT gate, three OR gates | |
| 45. |
Assume you have A, B, C, and D available but not their complements. The minimum number of 2-input NAND gates required to implement the equation is ________. |
| A. | 3 |
| B. | 4 |
| C. | 5 |
| D. | 6 |
| Answer» D. 6 | |
| 46. |
A 4-variable AND-OR circuit produces a 0 at its Y output. Which combination of inputs is correct? |
| A. | A = 0, B = 0, C = 1, D = 1 |
| B. | A = 1, B = 1, C = 0, D = 0 |
| C. | A = 1, B = 1, C = 1, D = 1 |
| D. | A = 1, B = 0, C = 1, D = 0 |
| Answer» E. | |
| 47. |
Implementing the expression AB + CDE using NAND logic, we get: |
| A. | (A) |
| B. | (B) |
| C. | (C) |
| D. | (D) |
| Answer» B. (B) | |
| 48. |
The output of an exclusive-NOR gate is 1. Which input combination is correct? |
| A. | A = 1, B = 0 |
| B. | A = 0, B = 1 |
| C. | A = 0, B = 0 |
| D. | none of the above |
| Answer» D. none of the above | |
| 49. |
To implement the expression , it takes one OR gate and ________. |
| A. | three AND gates and three inverters |
| B. | three AND gates and four inverters |
| C. | three AND gates |
| D. | one AND gate |
| Answer» B. three AND gates and four inverters | |
| 50. |
The output of a NAND gate is LOW when all inputs are HIGH at the same time. |
| A. | 1 |
| B. | |
| C. | 1 |
| D. | |
| Answer» B. | |