MCQOPTIONS
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MCQOPTIONS
This section includes 289 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Electronics knowledge and support exam preparation. Choose a topic below to get started.
| 101. |
What will be the starting address of memory chip, given that memory address of last location of an 1K byte memory chip is FBFFH? |
| A. | F800 H |
| B. | FA00H |
| C. | EB00H |
| D. | EBFFH |
| Answer» B. FA00H | |
| 102. |
The number of chips required to make up 1K-bytes of memory, if the available chip size is 256 1 bits |
| A. | 4 |
| B. | 8 |
| C. | 16 |
| D. | 32 |
| Answer» E. | |
| 103. |
The number of chips required to make up 16 K-bytes memory, if the available memory chip size is 2048 8 bits |
| A. | 4 |
| B. | 8 |
| C. | 16 |
| D. | 32 |
| Answer» C. 16 | |
| 104. |
The architecture of a PLA device differs from that of a PROM device in the following |
| A. | The former has a fixed OR array while the latter has a programmable OR array |
| B. | The former has a programmable AND array while the latter has a hard-wired AND array. |
| C. | The former has larger number of AND gates in the AND array than the latter for a given number of variables. |
| D. | The latter has a fixed OR array while the former has a programmable OR array. |
| Answer» B. The former has a programmable AND array while the latter has a hard-wired AND array. | |
| 105. |
A ROM is usually not preferred to implement those Boolean functions which |
| A. | Are very complex |
| B. | Can otherwise the implemented using a PLA |
| C. | Have a large number of don t care conditions |
| D. | Have large number of outputs |
| Answer» C. Have a large number of don t care conditions | |
| 106. |
It is desired to implement a binary multiplier capable of multiplying two 3-bit binary numbers. Size of ROM would be |
| A. | 64 4 |
| B. | 1024 6 |
| C. | 64 8 |
| D. | 128 6 |
| Answer» E. | |
| 107. |
A masked programmed version of PAL device that is pin compatible to its PAL counterpart is known as |
| A. | PLA device |
| B. | PAL device |
| C. | PLS device |
| D. | PGA device |
| Answer» D. PGA device | |
| 108. |
A programmable array logic (PAL) device has a |
| A. | Programmable AND-array at the input and a fixed OR-array at the output |
| B. | Fixed AND-array at the input and a programmable OR-array at the output |
| C. | Fixed AND-array at the input and a fixed OR-array at the output |
| D. | None of these |
| Answer» C. Fixed AND-array at the input and a fixed OR-array at the output | |
| 109. |
A PAL device is marked PAL-1618. It implies the following |
| A. | It has sixteen active-LOW inputs |
| B. | It has eight active-LOW outputs |
| C. | It has sixteen inputs and eight active-LOW outputs |
| D. | It has eight inputs and sixteen active-LOW outputs |
| Answer» B. It has eight active-LOW outputs | |
| 110. |
A PLA-like architecture that can implement a full adder should at least have |
| A. | Eight 6-input programmable AND gate, two 8-input programmable OR gates |
| B. | Seven 6-input programmable AND gates, two 4-input programmable OR Gates |
| C. | Eight 6-input programmable AND gates, two 4-input programmable OR gates |
| D. | Sixteen 3-input programmable AND gates, two 8- input programmable OR gates |
| Answer» E. | |
| 111. |
Size of the ROM required to implement a 16-to-1 multiplexer would be |
| A. | 512K 2 |
| B. | 1M 1 |
| C. | 1M 2 |
| D. | 256 2 |
| Answer» D. 256 2 | |
| 112. |
A PROM device that can generate any eight desired four-variable Boolean functions will have |
| A. | Four-2-inputs AND gates in the AND array and eight 8-input OR gates in the OR array. |
| B. | Eight 2-input AND gates in the AND array and eight 16 input OR gates in the OR array. |
| C. | Sixteen 2-inputs AND gates in the AND array and eight 16-input OR gates in the OR array. |
| D. | Sixteen 8-input AND gates in the AND array and eight 16-input OR gates in the OR array. |
| Answer» E. | |
| 113. |
Identify the programmable interconnect technology used in PLDs |
| A. | Antifuse |
| B. | Fuse |
| C. | Static RMA controlled switches |
| D. | All of these |
| Answer» E. | |
| 114. |
The most widely used hardware description language for describing digital designs on CPLD and FPGA devices is |
| A. | VHDL |
| B. | JAVA-HDL |
| C. | Verilog |
| D. | ABEL |
| Answer» B. JAVA-HDL | |
| 115. |
A programmable interconnect device that has high initial resistance and can be permanently programmed to highly conducting path is known as |
| A. | Fuse |
| B. | Floating-gate transistor |
| C. | Anti-fuse |
| D. | PGA device |
| Answer» C. Anti-fuse | |
| 116. |
Memory devices are used for |
| A. | Temporary storage of data |
| B. | Semi-permanent storage of data |
| C. | Permanent storage of data |
| D. | All of these |
| Answer» C. Permanent storage of data | |
| 117. |
Which one of the following types of RAM needs periodic refreshing |
| A. | Asynchronous SRAM |
| B. | DRAM |
| C. | Synchronous SRAM |
| D. | All types of RAM need periodic refreshing |
| Answer» D. All types of RAM need periodic refreshing | |
| 118. |
Three main building blocks of RAM are |
| A. | Array of memory cells, address decoder and read/write control logic |
| B. | Array of memory cells, input buffers and output buffers |
| C. | Array of memory cells, address decoder and buffers |
| D. | Address decoder, address encoder and memory cells |
| Answer» E. | |
| 119. |
Identify the primary memory device |
| A. | Registers built into the CPU |
| B. | RAM and ROM |
| C. | Cache memory |
| D. | All of these |
| Answer» C. Cache memory | |
| 120. |
A 16K RAM chip can stores |
| A. | 64000 bytes |
| B. | 65536 bytes |
| C. | 65536 bits |
| D. | 64000 bits |
| Answer» E. | |
| 121. |
Identify the characteristic feature or features of random access memory |
| A. | It is a serial access memory |
| B. | Data can be read from or written into any of the memory locations regardless order in which they are arranged |
| C. | All memory locations can be accessed with the same speed |
| D. | Both (B) and (C) |
| Answer» E. | |
| 122. |
With reference to erasable PROM devices, identify the true statement |
| A. | In the case of EEPROM selective erasure is not possible |
| B. | UV EPROM erasure process is very fast |
| C. | In the case of UV EPROM, selective erasure is not possible |
| D. | EEPROM has relatively much higher density as compared to UV EPROM. |
| Answer» D. EEPROM has relatively much higher density as compared to UV EPROM. | |
| 123. |
In volatile storage, data is lost |
| A. | Gradually with time |
| B. | As soon as saturation point is crossed |
| C. | As soon as programme is over |
| D. | When power is removed |
| Answer» E. | |
| 124. |
Memory that requires refreshing cycle is |
| A. | Dynamic MOS |
| B. | RAM |
| C. | ROM |
| D. | All of these |
| Answer» B. RAM | |
| 125. |
One of the following is true with respect to CPLD and FPGA devices |
| A. | CPLD architecture offers greater flexibility |
| B. | FPGA devices have very complex configurable logic blocks |
| C. | CPLD devices offer relatively lower flexibility but more predictable timing characteristics |
| D. | FPGA devices offer relatively lower flexibility but more predictable timing characteristics |
| Answer» C. CPLD devices offer relatively lower flexibility but more predictable timing characteristics | |
| 126. |
The primary memory of a computer system |
| A. | Holds the instructions of the program to be executed |
| B. | Stores data to be processed |
| C. | Stores the intermediate results of any calculation during processing of data |
| D. | All of these |
| Answer» B. Stores data to be processed | |
| 127. |
Which of the following is a permanent memory? |
| A. | RAM only |
| B. | ROM only |
| C. | Both RAM and ROM |
| D. | Neither RAM nor ROM |
| Answer» C. Both RAM and ROM | |
| 128. |
A temporary memory is |
| A. | Destroyed in few milliseconds |
| B. | Destroyed in few seconds |
| C. | Destroyed in few minutes |
| D. | Destroyed when power is switched off. |
| Answer» E. | |
| 129. |
Which of the following is a temporary memory? |
| A. | RAM only |
| B. | ROM only |
| C. | Both RAM and ROM |
| D. | Neither RAM nor ROM |
| Answer» B. ROM only | |
| 130. |
The abbreviation TTL stands for |
| A. | Transmitter transistor load |
| B. | Tuned transistor loop |
| C. | Transistor-transistor logic |
| D. | Transistor-transformer logic |
| Answer» D. Transistor-transformer logic | |
| 131. |
A Schmitt trigger |
| A. | Is a digital circuit that produces sinusoidal output regardless of the input waveform |
| B. | Is a digital circuit that produces rectangular output regardless of the input waveform |
| C. | Is a digital circuit that produces a trapezoidal output regardless of the input. |
| D. | None of these |
| Answer» C. Is a digital circuit that produces a trapezoidal output regardless of the input. | |
| 132. |
Indicate the false statement. The SWR on a transmission line if infinity the line is terminated in |
| A. | A short circuit |
| B. | A complex impedance |
| C. | An open circuit |
| D. | A pure reactance |
| Answer» C. An open circuit | |
| 133. |
With reference of a 2K bit ROM organized as 256 8 array of memory cells, which one of the following is true |
| A. | It uses 2000 memory cells |
| B. | It uses 256 rows of eight memory cells each |
| C. | It uses 2048 memory cells and 8 line to 256-line address decoder |
| D. | Both (B) and (C) are true |
| Answer» B. It uses 256 rows of eight memory cells each | |
| 134. |
The basic memory cell in a DRAM is a |
| A. | Capacitor |
| B. | MOS switch and a capacitor |
| C. | MOSFET |
| D. | Flip-flop |
| Answer» B. MOS switch and a capacitor | |
| 135. |
Resistor free logic |
| A. | TTL |
| B. | CMOS |
| C. | 4ns ECL |
| D. | 8ns ECL |
| Answer» C. 4ns ECL | |
| 136. |
SRAM devices are made using |
| A. | Bipolar, MOS or BICMOS technologies |
| B. | Bipolar technology |
| C. | MOS technology |
| D. | BICMOS technology |
| Answer» D. BICMOS technology | |
| 137. |
Logic with lowest power dissipation per gate is |
| A. | TTL |
| B. | CMOS |
| C. | 4ns ECL |
| D. | 8ns ECL |
| Answer» C. 4ns ECL | |
| 138. |
Logic with fan out of more than 50 is |
| A. | CMOS |
| B. | TTL |
| C. | 4ns ECL |
| D. | 8ns ECL |
| Answer» B. TTL | |
| 139. |
Fastest logic |
| A. | TTL |
| B. | LSI |
| C. | CMOS |
| D. | ECL |
| Answer» E. | |
| 140. |
Current-mode logic (CML) is the same as |
| A. | LSI |
| B. | CMOS |
| C. | TTL |
| D. | ECL |
| Answer» E. | |
| 141. |
The total number of inhibit drivers required for a 16K, 24- bit/word memory with a 3-D organization is |
| A. | 4 |
| B. | 8 |
| C. | 16 |
| D. | 24 |
| Answer» E. | |
| 142. |
For a 16K, 32-bit memory, the size of MBR register is |
| A. | 4 |
| B. | 16 |
| C. | 32 |
| D. | 64 |
| Answer» D. 64 | |
| 143. |
A microprocessor consists of a small number of LSI chips containing |
| A. | Control unit |
| B. | Logic unit |
| C. | Arithmetic unit |
| D. | All of the above |
| Answer» E. | |
| 144. |
A flip-flop free from race problem is |
| A. | JK flip-flop |
| B. | D flip-flop |
| C. | T flip-flop |
| D. | Master-slave flip-flop |
| Answer» E. | |
| 145. |
Which of the following ICs allow wired AND connections |
| A. | 7440 |
| B. | 8080 |
| C. | 7990 |
| D. | 7410 |
| Answer» B. 8080 | |
| 146. |
Which of the following name is associated with microprocessor manufacturer? |
| A. | Fairchild |
| B. | IBM |
| C. | Motorola |
| D. | Intel |
| Answer» E. | |
| 147. |
Intel 8080 has |
| A. | 16 pins |
| B. | 24 pins |
| C. | 32 pins |
| D. | 40 pins |
| Answer» E. | |
| 148. |
The unit of the speed of a digital IC is |
| A. | Hz |
| B. | kHz |
| C. | MHz |
| D. | GHz |
| Answer» D. GHz | |
| 149. |
Identify the IC with only one NAND gate? |
| A. | 7400 |
| B. | 7410 |
| C. | 7420 |
| D. | 7430 |
| Answer» E. | |
| 150. |
What is the minimum number of flip-flops required in a counter to count 60 pulses? |
| A. | 2 |
| B. | 4 |
| C. | 6 |
| D. | 8 |
| Answer» D. 8 | |