96 + Mcqs in Digital System Projects Using Hdl Page 1 McqOptions

1.	In the keypad encoder, the ring counter is implemented using ________ that responds to the input.
A.	SIGNAL
B.	FUNCTION
C.	CASE
D.	PROCESS
Answer» E.

Discussion

2.	In the keypad HDL encoder, the bit array represents a tristate buffer.
A.	True
B.	False
Answer» B. False

Discussion

3.	In the VHDL code of the stepper motor, the outputs are bit_vector type because they are binary bit patterns.
A.	True
B.	False
Answer» B. False

Discussion

4.	In the keypad application, when all columns are HIGH, the ring counter is enabled and counting, and is LOW, what is the status of the outputs?
A.	On
B.	Off
C.	Hi-Z
D.	1011
Answer» D. 1011

Discussion

5.	In the keypad application, just after the 4 ms mark the simulation imitates the release of the key by changing the column value back to F hex, which causes the output to go into its Hi-Z state. On the next rising clock edge, what happens to ?
A.	It goes HIGH.
B.	It goes LOW.
C.	It goes to Hi-Z.
D.	It goes to 1111H.
Answer» C. It goes to Hi-Z.

Discussion

6.	The full-step sequence always has two coils of the stepper motor energized in any state of the sequence and typically causes 30° of shaft rotation per step.
A.	True
B.	False
Answer» C.

Discussion

7.	The major blocks of the frequency counter are the counter, ________, decoder/display, and the timing and control unit.
A.	signal prescaler
B.	control inputs
C.	signal generator
D.	display register
Answer» E.

Discussion

8.	In the keypad encoder, the ________ activate(s) the freeze bit only when one column is low.
A.	NAND columns
B.	CASE structure
C.	freeze function
D.	BCD counter
Answer» C. freeze function

Discussion

9.	One aspect of project planning and management is the selection of ________ that will best fit the application.
A.	hardware platform
B.	software
C.	personnel
D.	time
Answer» B. software

Discussion

10.	In the keypad HDL encoder, as long as all columns are high the ring counter is enabled and counting.
A.	1
B.
Answer» B.

Discussion

11.	A very critical dimension in project management is the time your boss will give you to complete the HDL project.
A.	1
B.
Answer» B.

Discussion

12.	The step rate of the simulation of a stepper motor is probably ________ the actual stepper motor.
A.	slower than
B.	more than
C.	almost the same as
D.	exactly the same as
Answer» B. more than

Discussion

13.	In the digital clock project, the ENT input and RCO output can be used for synchronous counter cascading.
A.	1
B.
Answer» B.

Discussion

14.	The direct drive mode of a stepper motor allows for less control by the operator.
A.	1
B.
Answer» C.

Discussion

15.	In the keypad HDL encoder, the ts bit array represents a tristate buffer.
A.	1
B.
Answer» B.

Discussion

16.	In the frequency counter, the control clock is derived from the ________ by frequency dividers controlled in the control and timing block.
A.	BCD counters
B.	system clock signal
C.	display register
D.	decoder/display
Answer» C. display register

Discussion

17.	In the stepper motor, the half-step sequence is used when ________.
A.	less torque is needed
B.	larger steps are desired
C.	smaller steps are desirable
D.	more torque is needed
Answer» D. more torque is needed

Discussion

18.	A frequency counter is a circuit that can measure and display the frequency of a signal.
A.	1
B.
Answer» B.

Discussion

19.	In the keypad HDL encoder, the data signal is used to combine the row and column encoder data to make a 4-bit value representing the key that was pressed.
A.	1
B.
Answer» B.

Discussion

20.	In HDL when a circuit is simulated on a computer, the designer must create all the different scenarios that will be experienced by the actual circuit and must also know the proper response to those inputs.
A.	1
B.
Answer» B.

Discussion

21.	In the digital clock project, a 60 pps input is transformed into a 1 pps timing signal. The block is called ________.
A.	a BCD counter
B.	a MOD-60 counter
C.	frequency divider
D.	frequency prescaling
Answer» E.

Discussion

22.	Using one case construct inside another is known as ________.
A.	doping
B.	functioning
C.	freezing
D.	nesting
Answer» E.

Discussion

23.	One of the first steps in small-project management is to determine ________.
A.	how many devices are controlled by the outputs
B.	a way to test each block
C.	if each block fits together
D.	how each block works
Answer» B. a way to test each block

Discussion

24.	In the digital clock project HDL, the 1 pps signal is used as a synchronous clock for all of the counters' stages, which are synchronously cascaded.
A.	1
B.
Answer» B.

Discussion

25.	The wave-drive sequence of a stepper motor has more torque and operates more smoothly than the full-step sequence at moderate speeds.
A.	1
B.
Answer» C.

Discussion

26.	In the keypad HDL encoder, the freeze bit detects when a key is released.
A.	1
B.
Answer» C.

Discussion

27.	VARIABLES are considered to be updated ________ within a sequence of statements in a PROCESS, whereas SIGNALS referred to in a PROCESS are updated when the PROCESS ________.
A.	once, starts
B.	immediately, suspends
C.	twice, ends
D.	never, starts
Answer» C. twice, ends

Discussion

28.	In the keypad encoder, just after the 4 ms mark, the simulation initiates the release of the key by changing the column value to ________, which causes the d output to go into its Hi-Z state.
A.	0 hex
B.	4 hex
C.	8 hex
D.	F hex
Answer» E.

Discussion

29.	The full-step sequence of a stepper motor always has two coils energized in any state of the sequence and typically causes ________ of shaft rotation per step.
A.	5¬∞
B.	10¬∞
C.	15¬∞
D.	20¬∞
Answer» D. 20¬∞

Discussion

30.	In the digital clock project, the AHDL block codes are connected using graphic design files.
A.	1
B.
Answer» B.

Discussion

31.	In the keypad HDL encoder, NANDing of the columns is used to activate the freeze bit.
A.	1
B.
Answer» C.

Discussion

32.	In the digital clock project, when it is 11:59:59, AND gate 1 detects that the tens of hours is 1 and the enable input is active. On the next clock pulse the AM/PM flip-flop will ________.
A.	set
B.	reset
C.	toggle
D.	clear
Answer» D. clear

Discussion

33.	The stepper motor HDL will ignore its counter inputs and pass control inputs directly to the output when set in mode ________.
A.	1
B.	2
C.	3
D.	4
Answer» B. 2

Discussion

34.	In the frequency counter, a pulse shaper block is needed to ensure that the unknown signal, whose frequency is to be measured, will be compatible with the clock input for the counter block.
A.	1
B.
Answer» B.

Discussion

35.	In the digital clock project, the 60 Hz signal is sent through a Schmitt-trigger circuit to produce sine wave pulses at the rate of 60 pps.
A.	1
B.
Answer» C.

Discussion

36.	One CASE construct inside another CASE construct is called a do-loop.
A.	1
B.
Answer» C.

Discussion

37.	In the frequency counter, the length of time for the ________ to be enabled can be selected with the range select input.
A.	display register
B.	frequency prescaler
C.	BCD counter
D.	signal generator
Answer» D. signal generator

Discussion

38.	In a real project, the first step of definition often involves some ________ on the part of the project manager.
A.	time
B.	skill
C.	research
D.	management
Answer» D. management

Discussion

39.	In the digital clock design, the hours section is different from the seconds and minutes section in that it never goes to ________.
A.	the 0 state
B.	13
C.	the ring counter
D.	the BCD counter
Answer» B. 13

Discussion

40.	Depending on the ________ the IC is in, the output of the stepper motor HDL will respond to each pulse by changing state.
A.	mode
B.	make
C.	input
D.	output
Answer» B. make

Discussion

41.	In the frequency counter, the pulse width of the enable signal is very critical for taking an accurate frequency measurement.
A.	1
B.
Answer» B.

Discussion

42.	In the keypad HDL encoder, after releasing a key the ring counter resumes its counting sequence.
A.	1
B.
Answer» B.

Discussion

43.	The full-step sequence always has two coils of the stepper motor energized in any state of the sequence and typically causes 30¬∞ of shaft rotation per step.
A.	1
B.
Answer» C.

Discussion

44.	In the keypad encoder, the ________ detects when a key is pressed.
A.	ring counter
B.	MOD-6 counter
C.	BCD counter
D.	freeze bit
Answer» E.

Discussion

45.	Each ________, starting at the simplest level, should be built in HDL.
A.	subsystem
B.	block
C.	circuit
D.	function
Answer» B. block

Discussion

46.	In the VHDL code of the stepper motor, the cout outputs are bit_vector type because they are binary bit patterns.
A.	1
B.
Answer» B.

Discussion

47.	What must a stepper motor HDL application include?
A.	Variables and processes
B.	Types and bits
C.	Counters and decoders
D.	Sequencers and multiplexers
Answer» D. Sequencers and multiplexers

Discussion

48.	Which is not a step used to define the scope of an HDL project?
A.	Are the inputs and outputs active HIGH or active LOW?
B.	A clear vision of how to make each block work
C.	What are the speed requirements?
D.	How many bits of data are needed?
Answer» C. What are the speed requirements?

Discussion

49.	In the digital clock project, when it is 11:59:59, AND gate 1 detects that the tens of hours is 1 and the edge trigger clock moves the display to 12:00:00.
A.	1
B.
C.	1
D.
Answer» C. 1

Discussion

50.	When coming up with a strategy for dividing the overall project into manageable-size pieces one must ________.
A.	name each input and output
B.	fully understand how the device should operate
C.	define successful completion of the project
D.	know the nature of all the signals that interconnect all the pieces
Answer» E.

Discussion

Explore topic-wise MCQs in Digital Electronics.

In the keypad encoder, the ring counter is implemented using ________ that responds to the input.

In the keypad HDL encoder, the bit array represents a tristate buffer.

In the VHDL code of the stepper motor, the outputs are bit_vector type because they are binary bit patterns.

In the keypad application, when all columns are HIGH, the ring counter is enabled and counting, and is LOW, what is the status of the outputs?

In the keypad application, just after the 4 ms mark the simulation imitates the release of the key by changing the column value back to F hex, which causes the output to go into its Hi-Z state. On the next rising clock edge, what happens to ?

The full-step sequence always has two coils of the stepper motor energized in any state of the sequence and typically causes 30° of shaft rotation per step.

The major blocks of the frequency counter are the counter, ________, decoder/display, and the timing and control unit.

In the keypad encoder, the ________ activate(s) the freeze bit only when one column is low.

One aspect of project planning and management is the selection of ________ that will best fit the application.

In the keypad HDL encoder, as long as all columns are high the ring counter is enabled and counting.

A very critical dimension in project management is the time your boss will give you to complete the HDL project.

The step rate of the simulation of a stepper motor is probably ________ the actual stepper motor.

In the digital clock project, the ENT input and RCO output can be used for synchronous counter cascading.

The direct drive mode of a stepper motor allows for less control by the operator.

In the keypad HDL encoder, the ts bit array represents a tristate buffer.

In the frequency counter, the control clock is derived from the ________ by frequency dividers controlled in the control and timing block.

In the stepper motor, the half-step sequence is used when ________.

A frequency counter is a circuit that can measure and display the frequency of a signal.

In the keypad HDL encoder, the data signal is used to combine the row and column encoder data to make a 4-bit value representing the key that was pressed.

In HDL when a circuit is simulated on a computer, the designer must create all the different scenarios that will be experienced by the actual circuit and must also know the proper response to those inputs.

In the digital clock project, a 60 pps input is transformed into a 1 pps timing signal. The block is called ________.

Using one case construct inside another is known as ________.

One of the first steps in small-project management is to determine ________.

In the digital clock project HDL, the 1 pps signal is used as a synchronous clock for all of the counters' stages, which are synchronously cascaded.

The wave-drive sequence of a stepper motor has more torque and operates more smoothly than the full-step sequence at moderate speeds.

In the keypad HDL encoder, the freeze bit detects when a key is released.

VARIABLES are considered to be updated ________ within a sequence of statements in a PROCESS, whereas SIGNALS referred to in a PROCESS are updated when the PROCESS ________.

In the keypad encoder, just after the 4 ms mark, the simulation initiates the release of the key by changing the column value to ________, which causes the d output to go into its Hi-Z state.

The full-step sequence of a stepper motor always has two coils energized in any state of the sequence and typically causes ________ of shaft rotation per step.

In the digital clock project, the AHDL block codes are connected using graphic design files.

In the keypad HDL encoder, NANDing of the columns is used to activate the freeze bit.

In the digital clock project, when it is 11:59:59, AND gate 1 detects that the tens of hours is 1 and the enable input is active. On the next clock pulse the AM/PM flip-flop will ________.

The stepper motor HDL will ignore its counter inputs and pass control inputs directly to the output when set in mode ________.

In the frequency counter, a pulse shaper block is needed to ensure that the unknown signal, whose frequency is to be measured, will be compatible with the clock input for the counter block.

In the digital clock project, the 60 Hz signal is sent through a Schmitt-trigger circuit to produce sine wave pulses at the rate of 60 pps.

One CASE construct inside another CASE construct is called a do-loop.

In the frequency counter, the length of time for the ________ to be enabled can be selected with the range select input.

In a real project, the first step of definition often involves some ________ on the part of the project manager.

In the digital clock design, the hours section is different from the seconds and minutes section in that it never goes to ________.

Depending on the ________ the IC is in, the output of the stepper motor HDL will respond to each pulse by changing state.

In the frequency counter, the pulse width of the enable signal is very critical for taking an accurate frequency measurement.

In the keypad HDL encoder, after releasing a key the ring counter resumes its counting sequence.

The full-step sequence always has two coils of the stepper motor energized in any state of the sequence and typically causes 30¬∞ of shaft rotation per step.

In the keypad encoder, the ________ detects when a key is pressed.

Each ________, starting at the simplest level, should be built in HDL.

In the VHDL code of the stepper motor, the cout outputs are bit_vector type because they are binary bit patterns.

What must a stepper motor HDL application include?

Which is not a step used to define the scope of an HDL project?

In the digital clock project, when it is 11:59:59, AND gate 1 detects that the tens of hours is 1 and the edge trigger clock moves the display to 12:00:00.

When coming up with a strategy for dividing the overall project into manageable-size pieces one must ________.

VARIABLES are considered to be updated within a sequence of statements in a PROCESS, whereas SIGNALS referred to in a PROCESS are updated when the PROCESS .