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MCQOPTIONS
This section includes 194 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Electronics knowledge and support exam preparation. Choose a topic below to get started.
| 151. |
There are four possible combinations for subtracting two binary numbers. |
| A. | 1 |
| B. | |
| C. | 1 |
| D. | |
| Answer» B. | |
| 152. |
Subtraction of the 2's-complement system actually involves the operation of ________. |
| A. | multiplication |
| B. | subtraction |
| C. | addition |
| D. | division |
| Answer» D. division | |
| 153. |
What logic function is the sum output of a half-adder? |
| A. | AND |
| B. | exclusive-OR |
| C. | exclusive-NOR |
| D. | NAND |
| Answer» C. exclusive-NOR | |
| 154. |
The binary addition of 1 + 1 = ________. |
| A. | sum = 1carry = 1 |
| B. | sum = 0carry = 0 |
| C. | sum = 1carry = 0 |
| D. | sum = 0carry = 1 |
| Answer» E. | |
| 155. |
In VHDL, what is a GENERATE statement? |
| A. | The start statement of a program |
| B. | Not used in VHDL or ADHL |
| C. | A way to get the computer to generate a program from a circuit diagram |
| D. | A way to tell the compiler to replicate several components |
| Answer» E. | |
| 156. |
Add the following hexadecimal numbers. 3C   14   3B +25   +28   +DC |
| A. | 60    3C    116 |
| B. | 62    3C    118 |
| C. | 61    3C    117 |
| D. | 61    3D    117 |
| Answer» D. 61¬†¬†¬†¬†3D¬†¬†¬†¬†117 | |
| 157. |
The 74HC382 ALU can perform ________ operations. |
| A. | 2 |
| B. | 4 |
| C. | 8 |
| D. | 16 |
| Answer» D. 16 | |
| 158. |
Fast-look-ahead carry circuits found in most 4-bit full-adder circuits: |
| A. | determine sign and magnitude |
| B. | reduce propagation delay |
| C. | add a 1 to complemented inputs |
| D. | increase ripple delay |
| Answer» C. add a 1 to complemented inputs | |
| 159. |
What is one disadvantage of the ripple-carry adder? |
| A. | The interconnections are more complex. |
| B. | More stages are required to a full adder. |
| C. | It is slow due to propagation time. |
| D. | All of the above. |
| Answer» D. All of the above. | |
| 160. |
When 1100010 is divided by 0101, what is the decimal remainder? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 6 |
| Answer» C. 4 | |
| 161. |
If B[7..0] = 10100101, what is the value of B[6..2]? |
| A. | 10100 |
| B. | 1001 |
| C. | 10010 |
| D. | 101 |
| Answer» C. 10010 | |
| 162. |
What distinguishes the look-ahead-carry adder? |
| A. | It is slower than the ripple-carry adder. |
| B. | It is easier to implement logically than a full adder. |
| C. | It is faster than a ripple-carry adder. |
| D. | It requires advance knowledge of the final answer. |
| Answer» D. It requires advance knowledge of the final answer. | |
| 163. |
Hexadecimal is a base 4 numbering system. |
| A. | 1 |
| B. | |
| Answer» C. | |
| 164. |
How many inputs must a full-adder have? |
| A. | 4 |
| B. | 2 |
| C. | 5 |
| D. | 3 |
| Answer» E. | |
| 165. |
The decimal value for E16 is: |
| A. | 1210 |
| B. | 1310 |
| C. | 1410 |
| D. | 1510 |
| Answer» D. 1510 | |
| 166. |
Divide the following binary numbers. |
| A. | 0000  0010    0000  0010    1000  1111 |
| B. | 0000  0010    0001  0010    0000  0100 |
| C. | 0000  0011    0000  0010    0000  0100 |
| D. | 0000  0010    0000  0010    0000  0100 |
| Answer» E. | |
| 167. |
A half-adder circuit would normally be used each time a carry input is required in an adder circuit. |
| A. | 1 |
| B. | |
| C. | 1 |
| D. | |
| Answer» C. 1 | |
| 168. |
A full-adder adds ________. |
| A. | two single bits and one carry bit |
| B. | two 2-bit binary numbers |
| C. | two 4-bit binary numbers |
| D. | two 2-bit numbers and one carry bit |
| Answer» B. two 2-bit binary numbers | |
| 169. |
Adding in binary, a decimal 26 + 27 will produce a sum of: |
| A. | 111010 |
| B. | 110110 |
| C. | 110101 |
| D. | 101011 |
| Answer» D. 101011 | |
| 170. |
The range of negative numbers when using an eight-bit two's-complement system is –1 to –128. |
| A. | 1 |
| B. | |
| C. | 1 |
| D. | |
| Answer» B. | |
| 171. |
What are constants in VHDL code? |
| A. | Fixed numbers represented by a name |
| B. | Fixed variables used in functions |
| C. | Fixed number types |
| D. | Constants do not exist in VHDL code. |
| Answer» B. Fixed variables used in functions | |
| 172. |
When decimal numbers with several digits are to be added together using BCD adders ________. |
| A. | a separated BCD adder is required for each digit position |
| B. | the BCD adders must have the carry-outs grounded |
| C. | the BCD's must be grouped in twos |
| D. | full adders are also used |
| Answer» B. the BCD adders must have the carry-outs grounded | |
| 173. |
The carry propagation delay in 4-bit full-adder circuits: |
| A. | is cumulative for each stage and limits the speed at which arithmetic operations are performed |
| B. | is normally not a consideration because the delays are usually in the nanosecond range |
| C. | decreases in direct ratio to the total number of full-adder stages |
| D. | increases in direct ratio to the total number of full-adder stages, but is not a factor in limiting the speed of arithmetic operations |
| Answer» B. is normally not a consideration because the delays are usually in the nanosecond range | |
| 174. |
Could the sum output of a full-adder be used as a two-bit parity generator? |
| A. | Yes |
| B. | No |
| C. | The start statement of a program |
| D. | Not used in VHDL or ADHL |
| Answer» B. No | |
| 175. |
What is the first thing you will need if you are going to use a macrofunction? |
| A. | A complicated design project |
| B. | An experienced design engineer |
| C. | Good documentation |
| D. | Experience in HDL |
| Answer» D. Experience in HDL | |
| 176. |
If [A] = 1011 1010, [B] = 0011 0110, and [C] = [A] • [B], what is [C 4..2] in decimal? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» E. | |
| 177. |
Multiply the following binary numbers. 1010   1011   1001 ×0011   ×0111   ×1010 |
| A. | 0001  1110    0100  1101    0101  1011 |
| B. | 0001  1110    0100  1100    0101  1010 |
| C. | 0001  1110    0100  1101    0101  1010 |
| D. | 0001  1101    0100  1101    0101  1010 |
| Answer» D. 0001¬†¬†1101¬†¬†¬†¬†0100¬†¬†1101¬†¬†¬†¬†0101¬†¬†1010 | |
| 178. |
Which of the following is correct for full adders? |
| A. | Full adders have the capability of directly adding decimal numbers. |
| B. | Full adders are used to make half adders. |
| C. | Full adders are limited to two inputs since there are only two binary digits. |
| D. | In a parallel full adder, the first stage may be a half adder. |
| Answer» E. | |
| 179. |
In VHDL, the architecture declaration always begins with the ________ of variable signals or components that will be used in the concurrent description between BEGIN and END. |
| A. | type |
| B. | vectors |
| C. | functions |
| D. | declarations |
| Answer» E. | |
| 180. |
Which of the statements below best describes the given figure? |
| A. | Half-carry adder; Sum = 0, Carry = 1 |
| B. | Half-carry adder; Sum = 1, Carry = 0 |
| C. | Full-carry adder; Sum = 1, Carry = 0 |
| D. | Full-carry adder; Sum = 1, Carry = 1 |
| Answer» B. Half-carry adder; Sum = 1, Carry = 0 | |
| 181. |
Why is a fast-look-ahead carry circuit used in the 7483 4-bit full-adder? |
| A. | to decrease the cost |
| B. | to make it smaller |
| C. | to slow down the circuit |
| D. | to speed up the circuit |
| Answer» E. | |
| 182. |
The binary subtraction 0 – 0 = |
| A. | difference = 0borrow = 0 |
| B. | difference = 1borrow = 0 |
| C. | difference = 1borrow = 1 |
| D. | difference = 0borrow = 1 |
| Answer» B. difference = 1borrow = 0 | |
| 183. |
Solve this binary problem: 01110010 – 01001000 = |
| A. | 11010 |
| B. | 101010 |
| C. | 1110010 |
| D. | 111100 |
| Answer» C. 1110010 | |
| 184. |
Convert the decimal numbers 275 and 965 to binary-coded decimal (BCD) and add. Select the BCD code groups that reflect the final answer. |
| A. | 1101 1110 1010 |
| B. | 1110 1010 1110 |
| C. | 0001 0010 0100 0000 |
| D. | 0010 0011 0100 0000 |
| Answer» D. 0010 0011 0100 0000 | |
| 185. |
Subtract the following hexadecimal numbers. 47   34   FA –25   –1C   –2F |
| A. | 22    18    CB |
| B. | 22    17    CB |
| C. | 22    19    CB |
| D. | 22    18    CC |
| Answer» B. 22¬†¬†¬†¬†17¬†¬†¬†¬†CB | |
| 186. |
The most commonly used system for representing signed binary numbers is the: |
| A. | 2's-complement system. |
| B. | 1's-complement system. |
| C. | 10's-complement system. |
| D. | sign-magnitude system. |
| Answer» B. 1's-complement system. | |
| 187. |
An ALU is a multipurpose device capable of providing several different logic operations. |
| A. | 1 |
| B. | |
| C. | 1 |
| D. | |
| Answer» B. | |
| 188. |
A half-adder circuit would normally be used each time a carry input is required in an added circuit. |
| A. | 1 |
| B. | |
| C. | 10100 |
| D. | 1001 |
| Answer» C. 10100 | |
| 189. |
Solving –11 + (–2) will yield which two's-complement answer? |
| A. | 1110 1101 |
| B. | 1111 1001 |
| C. | 1111 0011 |
| D. | 1110 1001 |
| Answer» D. 1110 1001 | |
| 190. |
Convert each of the decimal numbers to two's-complement form and perform the addition in binary. +13 –10 add –7 add +15 |
| A. | 0001  0100    0000  0101 |
| B. | 0000  0110    0001  1001 |
| C. | 0000  0110    0000  0101 |
| D. | 1111  0110    1111  0101 |
| Answer» D. 1111¬†¬†0110¬†¬†¬†¬†1111¬†¬†0101 | |
| 191. |
Add the following BCD numbers. 0110   0111   1001 0101   1000   1000 |
| A. | 0000  1011    0000  1111    0001  0001 |
| B. | 0001  0001    0001  0101    0001  0001 |
| C. | 0000  1011    0000  1111    0001  0111 |
| D. | 0001  0001    0001  0101    0001  0111 |
| Answer» E. | |
| 192. |
Perform subtraction on each of the following binary numbers by taking the two's-complement of the number being subtracted and then adding it to the first number.01001        0110000011        00111 |
| A. | 01100    10011 |
| B. | 00110    00101 |
| C. | 10110    10101 |
| D. | 00111    00100 |
| Answer» C. 10110¬†¬†¬†¬†10101 | |
| 193. |
One way to make a four-bit adder perform subtraction is by: |
| A. | inverting the output. |
| B. | inverting the carry-in. |
| C. | inverting the B inputs. |
| D. | grounding the B inputs. |
| Answer» D. grounding the B inputs. | |
| 194. |
For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, the result is: |
| A. | the same as if the carry-in is tied LOW since the least significant carry-in is ignored. |
| B. | that carry-out will always be HIGH. |
| C. | a one will be added to the final result. |
| D. | the carry-out is ignored. |
| Answer» D. the carry-out is ignored. | |