99 + Mcqs in Shift Registers Page 1 McqOptions

1.	A type of shift register in which the Q or output of one stage is not connected to the input of the next stage is ________.
A.	parallel in/serial out
B.	serial in/parallel out
C.	serial in/serial out
D.	parallel in/parallel out
Answer» E.

Discussion

2.	Assume an 8-bit serial in/parallel out shift register needs to be cleared but has no clear input. How many clock cycles are required before a zero applied to the input appears on the Q output?
A.	1
B.	7
C.	8
D.	9
Answer» D. 9

Discussion

3.	An 8-bit serial in/parallel out shift register is clocked at 4 MHz and is used to delay a serial digital signal by 1.25 s. The output that has the proper delay is ________.
A.	Q
B.	Q
C.	Q
D.	Q
Answer» B. Q

Discussion

4.	In a parallel in/parallel out shift register, D = 1, D = 1, D = 1, and D = 0. After three clock pulses, the data outputs are ________.
A.	1110
B.	0001
C.	1100
D.	1000
Answer» C. 1100

Discussion

5.	A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________.
A.	1110
B.	0111
C.	1000
D.	1001
Answer» E.

Discussion

6.	When an 8-bit serial in/serial out shift register is used for a 20 s time delay, the clock frequency is ________.
A.	40 kHz
B.	50 kHz
C.	400 kHz
D.	500 kHz
Answer» D. 500 kHz

Discussion

7.	A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing ________.
A.	1101
B.	0111
C.	0001
D.	1110
Answer» C. 0001

Discussion

8.	When is LOW, the data are shifted one bit per clock pulse.
A.	True
B.	False
Answer» C.

Discussion

9.	There are several ways to construct a stepper motor to achieve digitally controlled stepping action. One possibility is to construct four stator coils set up as four pole pairs, each 45° apart and using three ferromagnetic pairs spaced 60° apart.
A.	True
B.	False
Answer» B. False

Discussion

10.	An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________
A.	16 us
B.	8 us
C.	4 us
D.	of ________a) 16 usb) 8 usc) 4 usd) 2 us
Answer» D. of ________a) 16 usb) 8 usc) 4 usd) 2 us

Discussion

11.	With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________
A.	4 μs
B.	40 μs
C.	400 μs
D.	40 ms
Answer» C. 400 μs

Discussion

12.	A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________
A.	0000
B.	1111
C.	0111
D.	1000
Answer» D. 1000

Discussion

13.	The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________
A.	01110
B.	00001
C.	00101
D.	00110
Answer» D. 00110

Discussion

14.	What is meant by the parallel load of a shift register?
A.	All FFs are preset with data
B.	Each FF is loaded with data, one at a time
C.	Parallel shifting of data
D.	All FFs are set with data
Answer» B. Each FF is loaded with data, one at a time

Discussion

15.	The full form of SIPO is ___________
A.	Serial-in Parallel-out
B.	Parallel-in Serial-out
C.	Serial-in Serial-out
D.	Serial-In Peripheral-Out
Answer» B. Parallel-in Serial-out

Discussion

16.	Based on how binary information is entered or shifted out, shift registers are classified into _______ categories.
A.	2
B.	3
C.	4
D.	5
Answer» D. 5

Discussion

17.	The ring and Johnson shift counters are uncommon circuits that are similar to synchronous counters.
A.	1
B.
Answer» C.

Discussion

18.	Bidirectional means having two states.
A.	1
B.
Answer» C.

Discussion

19.	Assume a 4-bit parallel in/serial out shift register is loaded with a binary number. How many clock pulses are required after the parallel load has occurred before the first bit in the sequence appears on the serial output line?
A.	0
B.	1
C.	2
D.	3
Answer» C. 2

Discussion

20.	To transmit parallel data over a serial cable, the data must first go through data conversion to the serial format.
A.	1
B.
Answer» B.

Discussion

21.	Eight states are in an 8-bit Johnson counter sequence.
A.	1
B.
Answer» C.

Discussion

22.	Using separate serial inputs for shifting left or shifting right is a major difference between the 74194 and other shift registers.
A.	1
B.
Answer» B.

Discussion

23.	A universal shift register has both serial and parallel input and output capacity.
A.	1
B.
Answer» B.

Discussion

24.	Parallel load means to load all flip-flops at the same time.
A.	1
B.
Answer» B.

Discussion

25.	Shifting a binary number to the left by one position is equivalent to ________.
A.	multiplying by two
B.	multiplying by four
C.	dividing by two
D.	dividing by four
Answer» B. multiplying by four

Discussion

26.	The 74194 4-bit bidirectional universal shift register has a wide range of applications.
A.	1
B.
Answer» B.

Discussion

27.	Assume a 4-bit Johnson counter is initially cleared. After the first clock pulse the output is 0001. After the next clock pulse the output will be ________.
A.	11
B.	10
C.	1000
D.	110
Answer» B. 10

Discussion

28.	A stage is two storage elements in a register.
A.	1
B.
Answer» C.

Discussion

29.	The storage capacity of a register makes it an important type of memory.
A.	1
B.
Answer» B.

Discussion

30.	When is LOW, the data are shifted one bit per clock pulse.
A.	1
B.
Answer» C.

Discussion

31.	Practically every possible load, shift, and conversion operation is available in a shift register IC.
A.	1
B.
Answer» B.

Discussion

32.	Assume an 8-bit serial in/parallel out shift register needs to be cleared but has no clear input. How many clock cycles are required before a zero applied to the input appears on the QH output?
A.	1
B.	7
C.	8
D.	9
Answer» D. 9

Discussion

33.	What is a recirculating register?
A.	serial out connected to serial in
B.	all Q outputs connected together
C.	a register that can be used over again
Answer» B. all Q outputs connected together

Discussion

34.	The primary purpose of a three-state buffer is usually:
A.	to provide isolation between the input device and the data bus
B.	to provide the sink or source current required by any device connected to its output without loading down the output device
C.	temporary data storage
D.	to control data flow
Answer» B. to provide the sink or source current required by any device connected to its output without loading down the output device

Discussion

35.	In a 74164 8-bit shift register, in order for the parallel data output to be synchronously loaded on the negative clock edge, the parallel enable input is LOW.
A.	1
B.
C.	1
D.
Answer» C. 1

Discussion

36.	A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?
A.	ring shift
B.	clock
C.	Johnson
D.	binary
Answer» B. clock

Discussion

37.	Computers operate on data internally in a ________ format.
A.	tristate
B.	universal
C.	parallel
D.	serial
Answer» D. serial

Discussion

38.	In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________.
A.	1110
B.	1
C.	1100
D.	1000
Answer» C. 1100

Discussion

39.	Which is not characteristic of a shift register?
A.	Serial in/parallel in
B.	Serial in/parallel out
C.	Parallel in/serial out
D.	Parallel in/parallel out
Answer» B. Serial in/parallel out

Discussion

40.	There are several ways to construct a stepper motor to achieve digitally controlled stepping action. One possibility is to construct four stator coils set up as four pole pairs, each 45¬∞ apart and using three ferromagnetic pairs spaced 60¬∞ apart.
A.	1
B.
Answer» B.

Discussion

41.	The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________.
A.	1110
B.	1
C.	101
D.	110
Answer» D. 110

Discussion

42.	What is the function of a buffer circuit?
A.	to provide an output that is inverted from that on the input
B.	to provide an output that is equal to its input
C.	to clean up the input
D.	to clean up the output
Answer» C. to clean up the input

Discussion

43.	An 8-bit serial in/parallel out shift register is clocked at 4 MHz and is used to delay a serial digital signal by 1.25 s. The output that has the proper delay is ________.
A.	QE
B.	QF
C.	QG
D.	QH
Answer» B. QF

Discussion

44.	When the output of a tristate shift register is disabled, the output level is placed in a:
A.	float state
B.	LOW state
C.	high-impedance state
D.	float or high-impedance state
Answer» E.

Discussion

45.	By adding recirculating lines to a 4-bit parallel-in, serial-out shift register, it becomes a ________, ________, and ________-out register.
A.	parallel-in, serial, parallel
B.	serial-in, parallel, serial
C.	series-parallel-in, series, parallel
D.	bidirectional in, parallel, series
Answer» B. serial-in, parallel, serial

Discussion

46.	Stepper motors have become popular in digital automation systems because ________.
A.	of their low cost
B.	they are driven by sequential digital signals
C.	they can be used to provide repetitive mechanical movement
D.	they are driven by sequential digital signals and can be used to provide repetitive mechanical movement
Answer» E.

Discussion

47.	How is a strobe signal used when serially loading a shift register?
A.	to turn the register on and off
B.	to control the number of clocks
C.	to determine which output Qs are used
D.	to determine the FFs that will be used
Answer» C. to determine which output Qs are used

Discussion

48.	An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output?
A.	1.67 s
B.	26.67 s
C.	26.7 ms
D.	267 ms
Answer» C. 26.7 ms

Discussion

49.	A 74HC195 4-bit parallel access shift register can be used for ________.
A.	serial in/serial out operation
B.	serial in/parallel out operation
C.	parallel in/serial out operation
D.	all of the above
Answer» E.

Discussion

50.	How much storage capacity does each stage in a shift register represent?
A.	One bit
B.	Two bits
C.	Four bits (one nibble)
D.	Eight bits (one byte)
Answer» B. Two bits

Discussion

Explore topic-wise MCQs in Digital Electronics.

A type of shift register in which the Q or output of one stage is not connected to the input of the next stage is ________.

Assume an 8-bit serial in/parallel out shift register needs to be cleared but has no clear input. How many clock cycles are required before a zero applied to the input appears on the Q output?

An 8-bit serial in/parallel out shift register is clocked at 4 MHz and is used to delay a serial digital signal by 1.25 s. The output that has the proper delay is ________.

In a parallel in/parallel out shift register, D = 1, D = 1, D = 1, and D = 0. After three clock pulses, the data outputs are ________.

A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________.

When an 8-bit serial in/serial out shift register is used for a 20 s time delay, the clock frequency is ________.

A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing ________.

When is LOW, the data are shifted one bit per clock pulse.

There are several ways to construct a stepper motor to achieve digitally controlled stepping action. One possibility is to construct four stator coils set up as four pole pairs, each 45° apart and using three ferromagnetic pairs spaced 60° apart.

An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________

With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________

A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________

The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________

What is meant by the parallel load of a shift register?

The full form of SIPO is ___________

Based on how binary information is entered or shifted out, shift registers are classified into _______ categories.

The ring and Johnson shift counters are uncommon circuits that are similar to synchronous counters.

Bidirectional means having two states.

Assume a 4-bit parallel in/serial out shift register is loaded with a binary number. How many clock pulses are required after the parallel load has occurred before the first bit in the sequence appears on the serial output line?

To transmit parallel data over a serial cable, the data must first go through data conversion to the serial format.

Eight states are in an 8-bit Johnson counter sequence.

Using separate serial inputs for shifting left or shifting right is a major difference between the 74194 and other shift registers.

A universal shift register has both serial and parallel input and output capacity.

Parallel load means to load all flip-flops at the same time.

Shifting a binary number to the left by one position is equivalent to ________.

The 74194 4-bit bidirectional universal shift register has a wide range of applications.

Assume a 4-bit Johnson counter is initially cleared. After the first clock pulse the output is 0001. After the next clock pulse the output will be ________.

A stage is two storage elements in a register.

The storage capacity of a register makes it an important type of memory.

When is LOW, the data are shifted one bit per clock pulse.

Practically every possible load, shift, and conversion operation is available in a shift register IC.

Assume an 8-bit serial in/parallel out shift register needs to be cleared but has no clear input. How many clock cycles are required before a zero applied to the input appears on the QH output?

What is a recirculating register?

The primary purpose of a three-state buffer is usually:

In a 74164 8-bit shift register, in order for the parallel data output to be synchronously loaded on the negative clock edge, the parallel enable input is LOW.

A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?

Computers operate on data internally in a ________ format.

In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________.

Which is not characteristic of a shift register?

There are several ways to construct a stepper motor to achieve digitally controlled stepping action. One possibility is to construct four stator coils set up as four pole pairs, each 45¬∞ apart and using three ferromagnetic pairs spaced 60¬∞ apart.

The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________.

What is the function of a buffer circuit?

An 8-bit serial in/parallel out shift register is clocked at 4 MHz and is used to delay a serial digital signal by 1.25 s. The output that has the proper delay is ________.

When the output of a tristate shift register is disabled, the output level is placed in a:

By adding recirculating lines to a 4-bit parallel-in, serial-out shift register, it becomes a ________, ________, and ________-out register.

Stepper motors have become popular in digital automation systems because ________.

How is a strobe signal used when serially loading a shift register?

An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output?

A 74HC195 4-bit parallel access shift register can be used for ________.

How much storage capacity does each stage in a shift register represent?

By adding recirculating lines to a 4-bit parallel-in, serial-out shift register, it becomes a , , and -out register.