MCQOPTIONS
Home
About Us
Contact Us
Bookmark
Saved Bookmarks
Testing Subject
General Aptitude
Logical and Verbal Reasoning
English Skills Ability
Technical Programming
Current Affairs
General Knowledge
Finance & Accounting
GATE (Mechanical Engineering)
Chemical Engineering
→
Digital Electronics
→
Integrated Circuit Technologies
→
When is LOW, the data are shifted one bit per clo...
1.
When is LOW, the data are shifted one bit per clock pulse.
A.
True
B.
False
Answer» C.
Show Answer
Discussion
No Comment Found
Post Comment
Related MCQs
A type of shift register in which the Q or output of one stage is not connected to the input of the next stage is ________.
Assume an 8-bit serial in/parallel out shift register needs to be cleared but has no clear input. How many clock cycles are required before a zero applied to the input appears on the Q output?
An 8-bit serial in/parallel out shift register is clocked at 4 MHz and is used to delay a serial digital signal by 1.25 s. The output that has the proper delay is ________.
In a parallel in/parallel out shift register, D = 1, D = 1, D = 1, and D = 0. After three clock pulses, the data outputs are ________.
A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________.
When an 8-bit serial in/serial out shift register is used for a 20 s time delay, the clock frequency is ________.
A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing ________.
When is LOW, the data are shifted one bit per clock pulse.
There are several ways to construct a stepper motor to achieve digitally controlled stepping action. One possibility is to construct four stator coils set up as four pole pairs, each 45° apart and using three ferromagnetic pairs spaced 60° apart.
An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________
Reply to Comment
×
Name
*
Email
*
Comment
*
Submit Reply
Your experience on this site will be improved by allowing cookies. Read
Cookie Policy
Reject
Allow cookies