MCQOPTIONS
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MCQOPTIONS
This section includes 204 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Electronics knowledge and support exam preparation. Choose a topic below to get started.
| 101. |
Address multiplexing is used to reduce the number of address lines. |
| A. | 1 |
| B. | |
| C. | 1 |
| D. | |
| Answer» B. | |
| 102. |
The number of 16k √ó 4 memories needed to construct a 128k √ó 8 memory is ________. |
| A. | 4 |
| B. | 8 |
| C. | 12 |
| D. | 16 |
| Answer» E. | |
| 103. |
ROMs are used to store data that generally cannot be easily changed. |
| A. | 1 |
| B. | |
| Answer» B. | |
| 104. |
What is the bit storage capacity of a ROM with a 1024 √ó 8 organization? |
| A. | 1024 |
| B. | 2048 |
| C. | 4096 |
| D. | 8192 |
| Answer» E. | |
| 105. |
To which pin on the RAM chip does the address decoder connect in order to signal which memory chip is being accessed? |
| A. | The address input |
| B. | The output enable |
| C. | The chip enable |
| D. | The data input |
| Answer» D. The data input | |
| 106. |
The bit capacity of a memory that has 2048 addresses and can store 8 bits at each address is ________. |
| A. | 4096 |
| B. | 8129 |
| C. | 16358 |
| D. | 32768 |
| Answer» D. 32768 | |
| 107. |
Microprocessors and memory ICs are generally designed to drive only a single TTL load. Therefore, if several inputs are being driven from the same bus, any memory IC must be ________. |
| A. | buffered |
| B. | decoded |
| C. | addressed |
| D. | stored |
| Answer» B. decoded | |
| 108. |
The TMS44100 has ________ address inputs. |
| A. | 10 |
| B. | 11 |
| C. | 12 |
| D. | 13 |
| Answer» C. 12 | |
| 109. |
Select the statement that best describes the fusible-link PROM. |
| A. | user-programmable, one-time programmable |
| B. | manufacturer-programmable, one-time programmable |
| C. | user-programmable, reprogrammable |
| D. | manufacturer-programmable, reprogrammable |
| Answer» B. manufacturer-programmable, one-time programmable | |
| 110. |
A FIFO ________. |
| A. | allows data to be clocked in and out at different clock rates |
| B. | outputs the data in the same order that it was input |
| C. | can be used to smooth out bursts of data into a continuous stream |
| D. | All of the above |
| Answer» E. | |
| 111. |
Which of the following memories is volatile? |
| A. | ROM |
| B. | EROM |
| C. | RAM |
| D. | Flash |
| Answer» D. Flash | |
| 112. |
Which of the following faults will the checkerboard pattern test for in RAM? |
| A. | Short between adjacent cells |
| B. | Ability to store both 0s and 1s |
| C. | Dynamically introduced errors between cells |
| D. | All of the above |
| Answer» E. | |
| 113. |
Which of the following describes the action of storing a bit of data in a mask ROM? |
| A. | A 1 is stored in a bipolar cell by opening the base connection to the address line. |
| B. | A 0 is stored in a bipolar cell by shorting the base connection to the address line. |
| C. | A 1 is stored by connecting the gate of a MOS cell to the address line. |
| D. | A 0 is stored by connecting the gate of a MOS cell to the address line. |
| Answer» D. A 0 is stored by connecting the gate of a MOS cell to the address line. | |
| 114. |
The difference between RAM and ROM is that ________. |
| A. | RAM has a read/write signal and ROM doesn't |
| B. | RAM will lose data when the power is removed and ROM won't |
| C. | RAM has random address access and ROM uses sequential address access |
| D. | RAM has a read/write signal and ROM doesn't; RAM will lose data when the power is removed and ROM won't. |
| Answer» E. | |
| 115. |
ROMs retain data when the ________. |
| A. | power is off |
| B. | power is on |
| C. | system is down |
| D. | all of the above |
| Answer» E. | |
| 116. |
Which of the following best describes volatile memory? |
| A. | memory that retains stored information when electrical power is removed |
| B. | memory that loses stored information when electrical power is removed |
| C. | magnetic memory |
| D. | nonmagnetic |
| Answer» C. magnetic memory | |
| 117. |
What is the major difference between SRAM and DRAM? |
| A. | DRAMs must be periodically refreshed. |
| B. | SRAMs can hold data via a static charge, even with power off. |
| C. | The only difference is the terminal from which the data is removed—from the FET Drain or Source. |
| D. | Dynamic RAMs are always active; static RAMs must reset between data read/write cycles. |
| Answer» B. SRAMs can hold data via a static charge, even with power off. | |
| 118. |
If a memory design allows a storage location to be accessed without first sequencing through other locations, it is called Random Access Memory. |
| A. | 1 |
| B. | |
| C. | 1 |
| D. | |
| Answer» B. | |
| 119. |
What is the difference between static RAM and dynamic RAM? |
| A. | Static RAM must be refreshed, dynamic RAM does not. |
| B. | There is no difference. |
| C. | Dynamic RAM must be refreshed, static RAM does not. |
| Answer» D. | |
| 120. |
How many address lines would be required for a 2K √ó 4 memory chip? |
| A. | 8 |
| B. | 10 |
| C. | 11 |
| D. | 12 |
| Answer» D. 12 | |
| 121. |
When a RAM module passes the checkerboard test it is: |
| A. | able to read and write only 1s. |
| B. | faulty. |
| C. | probably good. |
| D. | able to read and write only 0s. |
| Answer» D. able to read and write only 0s. | |
| 122. |
Which type of ROM can be erased by UV light? |
| A. | ROM |
| B. | mask ROM |
| C. | EPROM |
| D. | EEPROM |
| Answer» D. EEPROM | |
| 123. |
Why is a refresh cycle necessary for a dynamic RAM? |
| A. | to clear the flip-flops |
| B. | to set the flip-flops |
| C. | The refresh cycle discharges the capacitor cells. |
| D. | The refresh cycle keeps the charge on the capacitor cells. |
| Answer» E. | |
| 124. |
A nibble is a group of eight bits. |
| A. | 1 |
| B. | |
| C. | 1 |
| D. | |
| Answer» C. 1 | |
| 125. |
A type of memory that is accessed serially (one location after the other) is a ________. |
| A. | ROM |
| B. | read/write memory |
| C. | shift register |
| D. | PLD |
| Answer» D. PLD | |
| 126. |
The mask ROM is ________. |
| A. | MOS technology |
| B. | diode technology |
| C. | resistor-diode technology |
| D. | DROM technology |
| Answer» B. diode technology | |
| 127. |
Which of the following RAM timing parameters determine its operating speed? |
| A. | tACC |
| B. | tAA and tACS |
| C. | tCO and tOD |
| D. | tRC and tWC |
| Answer» E. | |
| 128. |
Address decoding for dynamic memory chip control may also be used for: |
| A. | controlling refresh circuits |
| B. | read and write control |
| C. | chip selection and address location |
| D. | memory mapping |
| Answer» D. memory mapping | |
| 129. |
Advantage(s) of an EEPROM over an EPROM is/are: |
| A. | the EPROM can be erased with ultraviolet light in much less time than an EEPROM |
| B. | the EEPROM can be erased and reprogrammed without removal from the circuit |
| C. | the EEPROM has the ability to erase and reprogram individual words |
| D. | the EEPROM can be erased and reprogrammed without removal from the circuit, and can erase and reprogram individual words |
| Answer» E. | |
| 130. |
When the term RAM is used with semiconductor memories, it usually means ________ as opposed to ROM. |
| A. | Random-Access Memory |
| B. | Read/Write Memory (RWM) |
| C. | flash memory |
| D. | temporary storage |
| Answer» C. flash memory | |
| 131. |
The ideal memory ________. |
| A. | has high storage capacity |
| B. | is nonvolatile |
| C. | has in-system read and write capacity |
| D. | has all of the above characteristics |
| Answer» E. | |
| 132. |
What is a major disadvantage of RAM? |
| A. | Its access speed is too slow. |
| B. | Its matrix size is too big. |
| C. | It is volatile. |
| D. | High power consumption |
| Answer» D. High power consumption | |
| 133. |
An 8-bit address code can select ________. |
| A. | 8 locations in memory |
| B. | 256 locations in memory |
| C. | 65,536 locations in memory |
| D. | 131,072 locations in memory |
| Answer» C. 65,536 locations in memory | |
| 134. |
Eight bits of digital data are normally referred to as a: |
| A. | group. |
| B. | byte. |
| C. | word. |
| D. | cell. |
| Answer» C. word. | |
| 135. |
Information that is stored in an EEPROM ________. |
| A. | can be modified by performing a memory write operation |
| B. | is stored by the manufacturer and cannot be changed |
| C. | is lost if power is interrupted |
| D. | can be erased by applying high voltage to each storage location |
| Answer» E. | |
| 136. |
FIFO is formed by an arrangement of ________. |
| A. | diodes |
| B. | transistors |
| C. | MOS cells |
| D. | shift registers |
| Answer» E. | |
| 137. |
A burst refresh and a normal memory operation of a DRAM can be interspersed. |
| A. | 1 |
| B. | |
| Answer» C. | |
| 138. |
The RAM circuit given below is suspected of being bad. A check with a logic probe shows pulse activity on all of the address lines and data inputs. The / line and inputs are forced HIGH and the data output lines are checked with the logic probe. Q0, Q2, and Q3 show a dim indication on the logic probe; Q1 indicates a HIGH level on the logic probe. What, if anything, is wrong with the circuit? |
| A. | The Q0, Q2, and Q3 output lines are open; the chip is defective. |
| B. | The Q1 line appears to be shorted to Vcc; replace the chip. |
| C. | The outputs should be active only when the / line is held LOW, so the circuit is behaving normally considering the fact that the line is HIGH. |
| D. | The EN input should be forced HIGH and the outputs rechecked; if they are still giving the same indications as before, then the three outputs are definitely open and the IC will have to be replaced. |
| Answer» C. The outputs should be active only when the / line is held LOW, so the circuit is behaving normally considering the fact that the line is HIGH. | |
| 139. |
For the given circuit, what memory location is being addressed? |
| A. | 10111 |
| B. | 249 |
| C. | 5 |
| D. | 157 |
| Answer» C. 5 | |
| 140. |
The time from the beginning of a read cycle to the end of tACS or tAA is referred to as: |
| A. | access time |
| B. | data hold |
| C. | read cycle time |
| D. | write enable time |
| Answer» B. data hold | |
| 141. |
Which of the following best describes EPROMs? |
| A. | EPROMs can be programmed only once. |
| B. | EPROMs can be erased by UV. |
| C. | EPROMs can be erased by shorting all inputs to the ground. |
| D. | All of the above. |
| Answer» C. EPROMs can be erased by shorting all inputs to the ground. | |
| 142. |
One of the most important specifications on magnetic media is the ________. |
| A. | rotation speed |
| B. | tracks per inch |
| C. | data transfer rate |
| D. | polarity reversal rate |
| Answer» D. polarity reversal rate | |
| 143. |
Suppose that a certain semiconductor memory chip has a capacity of 8K √ó 8. How many bytes could be stored in this device? |
| A. | 8000 |
| B. | 64000 |
| C. | 65536 |
| D. | 8192 |
| Answer» E. | |
| 144. |
Which type of ROM has to be custom built by the factory? |
| A. | ROM |
| B. | mask ROM |
| C. | EPROM |
| D. | EEPROM |
| Answer» C. EPROM | |
| 145. |
What two functions does a DRAM controller perform? |
| A. | address multiplexing and data selection |
| B. | address multiplexing and the refresh operation |
| C. | data selection and the refresh operation |
| D. | data selection and CPU accessing |
| Answer» C. data selection and the refresh operation | |
| 146. |
Which is not a magnetic storage device? |
| A. | Magnetic disk |
| B. | Magnetic tape |
| C. | Magneto-optical disk |
| D. | Optical disk |
| Answer» E. | |
| 147. |
The EPROM is strictly a MOS device. |
| A. | 1 |
| B. | |
| C. | 1 |
| D. | |
| Answer» B. | |
| 148. |
What is the principal advantage of using address multiplexing with DRAM memory? |
| A. | reduced memory access time |
| B. | reduced requirement for constant refreshing of the memory contents |
| C. | reduced pin count and decrease in package size |
| D. | It eliminates the requirement for a chip-select input line, thereby reducing the pin count. |
| Answer» D. It eliminates the requirement for a chip-select input line, thereby reducing the pin count. | |
| 149. |
Which of the following memories uses a MOS capacitor as its memory cell? |
| A. | SRAM |
| B. | DRAM |
| C. | ROM |
| D. | FIFO |
| Answer» C. ROM | |
| 150. |
What is a multitap digital delay line? |
| A. | a series of inverter gates with RC circuits between each one |
| B. | a series of inverter gates with RL circuits between each one |
| C. | a series of NAND gates with RC circuits between each one |
| D. | a series of NAND gates with RL circuits between each one |
| Answer» B. a series of inverter gates with RL circuits between each one | |