Explore topic-wise MCQs in Digital Electronics.

This section includes 190 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Electronics knowledge and support exam preparation. Choose a topic below to get started.

151.

Which segments of a seven-segment display would be required to be active to display the decimal digit 2?

A. a, b, d, e, and g
B. a, b, c, d, and g
C. a, c, d, f, and g
D. a, b, c, d, e, and f
Answer» B. a, b, c, d, and g
Discussion
152.

What is the difference between a 7490 and a 7492?

A. 7490 is a MOD-12, 7492 is a MOD-10
B. 7490 is a MOD-12, 7492 is a MOD-16
C. 7490 is a MOD-16, 7492 is a MOD-10
D. 7490 is a MOD-10, 7492 is a MOD-12
Answer» E.
Discussion
153.

The MOD number of a Johnson counter will always be equal to one-half the number of flip-flops in the counter.

A. 1
B.
Answer» C.
Discussion
154.

A BCD counter is a ________.

A. binary counter
B. full-modulus counter
C. decade counter
D. divide-by-10 counter
Answer» D. divide-by-10 counter
Discussion
155.

How many natural states will there be in a 4-bit ripple counter?

A. 4
B. 8
C. 16
D. 32
Answer» D. 32
Discussion
156.

A MOD-16 synchronous counter has inputs labeled . These inputs would most probably be used to:

A. reset the counter to 0000 at the end of each count cycle
B. preset the counter to a value determined by the inputs any time the is active-HIGH
C. preset the counter to a value determined by the inputs any time the is active-LOW
D. reset the counter to 0000 any time is active-HIGH and is active-LOW
Answer» E.
Discussion
157.

Referring to the given figure, what causes the Control FF to reset after D7?

A. Once the data cycle is initiated by the Start bit, the one-shot produces an output pulse equal to the duration of the eight data bits. Once the eight data bits have been transferred to the data input register, the falling edge of the one-shot pulse resets the Control FF to start the sequence all over again.
B. After counting the eight data bits, the divide-by-8 counter produces an output on its active-LOW CLR line to reset the Control FF.
C. After counting eight clock pulses equivalent to eight data periods, the terminal count of the divide-by-8 counter and the clock trigger the one-shot, which in turn resets the Control FF and divide-by-8 circuits to begin the sequence all over again. Simultaneously the data is transferred through the output register.
D. When the data output register is full, it produces an output on its C terminal that triggers the one-shot, which in turn resets the Control FF.
Answer» D. When the data output register is full, it produces an output on its C terminal that triggers the one-shot, which in turn resets the Control FF.
Discussion
158.

How many data bits can be stored in the register shown below?

A. 5
B. 32
C. 31
D. 4
Answer» B. 32
Discussion
159.

One characteristic of a ring counter is that the modulus is equal to the number of flip-flops in the register and, consequently, there are never any unused or invalid states.

A. 1
B.
C. 1
D.
Answer» C. 1
Discussion
160.

Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:

A. input clock pulses are applied only to the first and last stages.
B. input clock pulses are applied only to the last stage.
C. input clock pulses are applied simultaneously to each stage.
D. input clock pulses are not used to activate any of the counter stages.
Answer» D. input clock pulses are not used to activate any of the counter stages.
Discussion
161.

The hexadecimal equivalent of 15,536 is ________.

A. 3CB0
B. 3C66
C. 63C0
D. 6300
Answer» B. 3C66
Discussion
162.

Three cascaded modulus-5 counters have an overall modulus of ________.

A. 5
B. 25
C. 125
D. 500
Answer» D. 500
Discussion
163.

For a one-shot application, how can HDL code be used to make a circuit respond once to each positive transition on its trigger input?

A. By using a counter
B. By using an active clock
C. By using an immediate reload
D. By using edge trapping
Answer» E.
Discussion
164.

How many different states does a 3-bit asynchronous counter have?

A. 2
B. 4
C. 8
D. 16
Answer» D. 16
Discussion
165.

It is a characteristic of ring counters that the ________ equal to the number of flip-flops in the register.

A. number of invalid states is
B. number of CASE statements is
C. modulus is
D. other states are
Answer» D. other states are
Discussion
166.

An effective time delay device can be constructed by using the propagation delay characteristic of parallel shift registers.

A. 1
B.
C. 1
D.
Answer» C. 1
Discussion
167.

Synchronous construction reduces the delay time of a counter to the delay of:

A. all flip-flops and gates
B. all flip-flops and gates after a 3 count
C. a single gate
D. a single flip-flop and a gate
Answer» E.
Discussion
168.

A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________.

A. 15 ns
B. 30 ns
C. 45 ns
D. 60 ns
Answer» E.
Discussion
169.

One method of troubleshooting involves ________ the circuit under test with a ________ or ________ and then observing the output to check for proper bit patterns.

A. checking, voltmeter, ohmmeter
B. exercising, stimulus, test pattern
C. testing, scope, logic analyzer
D. smashing, hammer, axe
Answer» C. testing, scope, logic analyzer
Discussion
170.

________ counters are often used whenever pulses are to be counted and the results displayed in decimal.

A. Synchronous
B. Bean
C. Decade
D. BCD
Answer» E.
Discussion
171.

Select the response that best describes the use of the Master Reset on typical 4-bit binary counters.

A. When MR1 and MR2 are both HIGH, all Qs will be reset to zero.
B. When MR1 and MR2 are both HIGH, all Qs will be reset to one.
C. MR1 and MR2 are provided to synchronously reset all four flip-flops.
D. To enable the count mode, MR1 and MR2 must be held LOW.
Answer» B. When MR1 and MR2 are both HIGH, all Qs will be reset to one.
Discussion
172.

A counter with a modulus of 16 acts as a ________.

A. divide-by-8 counter
B. divide-by-16 counter
C. divide-by-32 counter
D. divide-by-64 counter
Answer» C. divide-by-32 counter
Discussion
173.

Using four cascaded counters with a total of 16 bits, how many states must be deleted to achieve a modulus of 50,000?

A. 50000
B. 65536
C. 25536
D. 15536
Answer» E.
Discussion
174.

How can a digital one-shot be implemented using HDL?

A. By using a resistor and a capacitor
B. By applying the concept of a counter
C. By using a library function
D. By applying a level trigger
Answer» C. By using a library function
Discussion
175.

A reliable method for eliminating decoder spikes is the technique called ________.

A. strobing
B. feeding
C. wagging
D. waving
Answer» B. feeding
Discussion
176.

A principle regarding most display decoders is that when the correct input is present, the related output will switch:

A. HIGH
B. to high impedance
C. to an open
D. LOW
Answer» E.
Discussion
177.

List which pins need to be connected together on a 7493 to make a MOD-12 counter.

A. 12 to 1, 11 to 3, 9 to 2
B. 12 to 1, 11 to 3, 12 to 2
C. 12 to 1, 11 to 3, 8 to 2
D. 12 to 1, 11 to 3, 1 to 2
Answer» D. 12 to 1, 11 to 3, 1 to 2
Discussion
178.

The circuit given below has no output on Q1 when examined with an oscilloscope. All J-K inputs are HIGH, the CLK signal is present, and the Q0 is toggling. The C input of FF1 is a constant LOW. What could be causing the problem?

A. The Q0 output should be connected to the J input of FF1.
B. The output of FF0 may be shorted to ground.
C. The input of FF1 may be shorted to ground.
D. Either the output of FF0 or the input of FF1 may be shorted to ground.
Answer» E.
Discussion
179.

What function does the CTR DIV 8 circuit given below perform?

A. It divides the clock frequency down to match the frequency of the serial data in.
B. The divide-by-8 counter is triggered by the control flip-flop and clock, which then allows the data output register to begin storing the input data. Once all eight data bits are stored in the data output register, the data output register and the divide-by-8 counter trigger the one-shot. The one-shot then begins the process all over again.
C. The divide-by-8 counter is used to verify that the parity bit is attached to the input data string.
D. It keeps track of the eight data bits, triggering the transfer of the data through the output register and the one-shot, which then resets the control flip-flop and divide-by-8 counter.
Answer» E.
Discussion
180.

Which of the following statements best describes the operation of a synchronous up-/down-counter?

A. The counter can count in either direction, but must continue in that direction once started.
B. The counter can be reversed, but must be reset before counting in the other direction.
C. In general, the counter can be reversed at any point in its counting sequence.
D. The count sequence cannot be reversed, once it has begun, without first resetting the counter to zero.
Answer» D. The count sequence cannot be reversed, once it has begun, without first resetting the counter to zero.
Discussion
181.

MOD-6 and MOD-12 counters and multiples are most commonly used as:

A. frequency counters
B. multiplexed displays
C. digital clocks
D. power consumption meters
Answer» D. power consumption meters
Discussion
182.

When two counters are cascaded, the overall MOD number is equal to the ________ of their individual MOD numbers.

A. product
B. sum
C. log
D. reciprocal
Answer» B. sum
Discussion
183.

Bidirectional shift registers can shift data either right or left.

A. 1
B.
C. 1
D.
Answer» B.
Discussion
184.

A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state does the counter go on the next clock pulse?

A. 1101
B. 1011
C. 1111
D. 0
Answer» C. 1111
Discussion
185.

A MOD-16 ripple counter is holding the count 10012. What will the count be after 31 clock pulses?

A. 10002
B. 10102
C. 10112
D. 11012
Answer» B. 10102
Discussion
186.

The terminal count of a modulus-11 binary counter is ________.

A. 1010
B. 1000
C. 1001
D. 1100
Answer» B. 1000
Discussion
187.

What type of device is shown below?

A. 4-bit bidirectional universal shift register
B. Parallel in/parallel out shift register with bidirectional data flow
C. 2-way parallel in/serial out bidirectional register
D. 2-bit serial in/4-bit parallel out bidirectional shift register
Answer» B. Parallel in/parallel out shift register with bidirectional data flow
Discussion
188.

Integrated-circuit counter chips are used in numerous applications including:

A. timing operations, counting operations, sequencing, and frequency multiplication
B. timing operations, counting operations, sequencing, and frequency division
C. timing operations, decoding operations, sequencing, and frequency multiplication
D. data generation, counting operations, sequencing, and frequency multiplication
Answer» C. timing operations, decoding operations, sequencing, and frequency multiplication
Discussion
189.

Which of the following procedures could be used to check the parallel loading feature of a counter?

A. Preset the LOAD inputs, set the CLR to its active level, and check to see that the Q outputs match the values preset into the LOAD inputs.
B. Apply LOWs to the parallel DATA inputs, pulse the CLK input, and check for LOWs on all the Q outputs.
C. Apply HIGHs to all the DATA inputs, pulse the CLK and CLR inputs, and check to be sure that the Q outputs are all LOW.
D. Apply HIGHs to all the Q terminals, pulse the CLK, and check to see if the DATA terminals now match the Q outputs.
Answer» C. Apply HIGHs to all the DATA inputs, pulse the CLK and CLR inputs, and check to be sure that the Q outputs are all LOW.
Discussion
190.

How many flip-flops are required to make a MOD-32 binary counter?

A. 3
B. 45
C. 5
D. 6
Answer» D. 6
Discussion