190 + Mcqs in Counters Page 2 McqOptions

51.	The technique used by one-shots to respond to an edge rather than a level is called ________.
A.	level management
B.	edge triggering
C.	trigger input
D.	edge trapping
Answer» B. edge triggering

Discussion

52.	In order to use a shift register as a counter, ________.
A.	the register's serial input is the counter input and the serial output is the counter output
B.	the parallel inputs provide the input signal and the output signal is taken from the serial data output
C.	serial in/serial out register must be used
D.	the serial output of the register is connected back to the serial input of the register
Answer» E.

Discussion

53.	Shift-register counters use ________, which means that the output of the last FF in the register is connected back to the first FF in some way.
A.	MOD
B.	feedback
C.	strobing
D.	switchbacks
Answer» C. strobing

Discussion

54.	The minimum number of flip-flops that can be used to construct a modulus-5 counter is ________.
A.	3
B.	5
C.	8
D.	10
Answer» B. 5

Discussion

55.	The terminal marked A on the CTR block in the given figure is the SET terminal.
A.	1
B.
Answer» C.

Discussion

56.	________ is the modulus of the counter shown below.
A.	200
B.	19
C.	0.005
D.	5000
Answer» B. 19

Discussion

57.	A glitch is a short pulse resulting in an undesired result in a digital circuit.
A.	1
B.
Answer» B.

Discussion

58.	All flip-flops in an asynchronous counter change states at the same time.
A.	1
B.
Answer» C.

Discussion

59.	Many parallel counters use ________ presetting whereby the counter is preset on the active transition of the same clock signal that is used for counting.
A.	feedback
B.	synchronous
C.	ripple
D.	asynchronous
Answer» C. ripple

Discussion

60.	In a synchronous counter, each state is clocked by the same pulse.
A.	1
B.
Answer» B.

Discussion

61.	The serial in/parallel out shift register transfers data from one parallel data bus to another parallel data bus one bit at a time across a single line.
A.	1
B.
Answer» C.

Discussion

62.	Another term used to describe up/down counters is bidirectional.
A.	1
B.
Answer» B.

Discussion

63.	An asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be changed to a down counter by ________.
A.	taking the output on the other side of the flip-flops ( instead of Q)
B.	clocking of each succeeding flip-flop from the other side ( instead of Q)
C.	changing the flip-flops to trailing edge triggering
D.	all of the above
Answer» E.

Discussion

64.	The circuit shown below is a ________.
A.	parallel in/serial out register
B.	serial in/parallel load register
C.	multiplexer
D.	demultiplexer
Answer» B. serial in/parallel load register

Discussion

65.	In a 74192 BCD decade up-/down-counter, the terminal count up and the terminal count down are active-LOW.
A.	1
B.
Answer» B.

Discussion

66.	Assume a 4-bit ripple counter has a failure in the second flip-flop such that it "locks up." The third and fourth stages will ________.
A.	continue to count with correct outputs
B.	continue to count but have incorrect outputs
C.	stop counting
D.	turn into molten silicon
Answer» D. turn into molten silicon

Discussion

67.	A reliable method for eliminating decoder spikes is to use strobing.
A.	1
B.
Answer» B.

Discussion

68.	In general, when using a scope to troubleshoot digital systems the instrument should be triggered by ________.
A.	the A channel or channel 1
B.	the vertical input mode, when using more than one channel
C.	the system clock
D.	line sync, in order to observe troublesome power line glitches
Answer» D. line sync, in order to observe troublesome power line glitches

Discussion

69.	The given circuit is a(n) ________.
A.	three-bit synchronous binary counter
B.	eight-bit asynchronous binary flip-flop
C.	two-bit asynchronous binary counter
D.	four-bit asynchronous binary counter
Answer» E.

Discussion

70.	Cascade means to connect the Q output of one flip-flop to the clock input of the next.
A.	1
B.
Answer» B.

Discussion

71.	In a full-featured counter in HDL, the concept of rolling over simply means the count sequence has reached its limit and must start over at the beginning of the sequence.
A.	1
B.
Answer» B.

Discussion

72.	A sequential circuit design is used to ________.
A.	count up
B.	count down
C.	decode an end count
D.	count in a random order
Answer» E.

Discussion

73.	A J-K flip-flop is reset and must stay reset after the clock pulse. This transition requires that ________.
A.	J and K inputs must both = 0
B.	J must be 0, K doesn't matter
C.	J doesn't matter, K must = 0
D.	J must be 0 and K must be 1
Answer» C. J doesn't matter, K must = 0

Discussion

74.	The 7447 has a 4-bit BCD input, seven individual active-LOW outputs, and a ripple blanking input and output.
A.	1
B.
Answer» B.

Discussion

75.	The MOD-10 counter is also referred to as a ________ counter.
A.	decade
B.	strobing
C.	BCD
D.	circuit
Answer» B. strobing

Discussion

76.	A serial in/serial out shift register transfers data from one line of a parallel bus to another line one bit at a time.
A.	1
B.
Answer» C.

Discussion

77.	The term synchronous refers to events that do not occur at the same time.
A.	1
B.
Answer» C.

Discussion

78.	The circuit shown below is used for ________, and for the inputs shown, the DATA output will be ________.
A.	multiplexing, 1
B.	parallel-to-serial conversion, 0
C.	demultiplexing, 0
D.	parallel-to-serial conversion, HIGH
Answer» C. demultiplexing, 0

Discussion

79.	Phototransistors have varying resistance from collector to emitter, depending on how much light strikes them.
A.	1
B.
Answer» B.

Discussion

80.	A D flip-flop can be made to toggle by ________.
A.	connecting to Q to D
B.	connecting to Q to D
C.	connecting D low
D.	connecting D high
Answer» B. connecting to Q to D

Discussion

81.	The modulus of a counter is the actual number of states in its sequence.
A.	1
B.
Answer» B.

Discussion

82.	Asynchronous counters are often called ________ counters.
A.	toggle
B.	ripple
C.	binary
D.	flip-flop
Answer» C. binary

Discussion

83.	When a J-K flip-flop is used in a circuit, we only have to consider the level at J and K at the active clock edge to know the states of the outputs.
A.	1
B.
Answer» C.

Discussion

84.	A multiplexed display being driven by a logic circuit:
A.	accepts data inputs from one line and passes this data to multiple output lines
B.	accepts data inputs from several lines and allows one of them at a time to pass to the output
C.	accepts data inputs from multiple lines and passes this data to multiple output lines
D.	accepts data inputs from several lines and multiplexes this input data to four BCD lines
Answer» C. accepts data inputs from multiple lines and passes this data to multiple output lines

Discussion

85.	Any divide-by-N counter can be formed by using external gating to ________ at a predetermined number.
A.	HIGH
B.	reset
C.	LOW
D.	preset
Answer» C. LOW

Discussion

86.	A 4-bit counter has a maximum modulus of ________.
A.	3
B.	6
C.	8
D.	16
Answer» E.

Discussion

87.	What is the difference between combinational logic and sequential logic?
A.	Combinational circuits are not triggered by timing pulses, sequential circuits are triggered by timing pulses.
B.	Combinational and sequential circuits are both triggered by timing pulses.
C.	Neither circuit is triggered by timing pulses.
Answer» B. Combinational and sequential circuits are both triggered by timing pulses.

Discussion

88.	To design a divide-by-200 counter using synchronous counters, two 4-bit counters could be cascaded together to form an 8-bit counter.
A.	1
B.
C.	1
D.
Answer» B.

Discussion

89.	The process of designing a synchronous counter that will count in a nonbinary manner is primarily based on:
A.	external logic circuits that decode the various states of the counter to apply the correct logic levels to the J-K inputs
B.	modifying BCD counters to change states on every second input clock pulse
C.	modifying asynchronous counters to change states on every second input clock pulse
D.	elimination of the counter stages and the addition of combinational logic circuits to produce the desired counts
Answer» B. modifying BCD counters to change states on every second input clock pulse

Discussion

90.	A ripple counter's speed is limited by the propagation delay of:
A.	each flip-flop
B.	all flip-flops and gates
C.	the flip-flops only with gates
D.	only circuit gates
Answer» B. all flip-flops and gates

Discussion

91.	One of the major drawbacks to the use of asynchronous counters is:
A.	low-frequency applications are limited because of internal propagation delays
B.	high-frequency applications are limited because of internal propagation delays
C.	asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications
D.	asynchronous counters do not have propagation delays and this limits their use in high-frequency applications
Answer» C. asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications

Discussion

92.	Referring to the given figure, at which point is the serial data transferred to the parallel output?
A.	W
B.	X
C.	Y
D.	Z
Answer» E.

Discussion

93.	A four-channel scope is used to check the counter in the figure given below. Are the displayed waveforms correct?
A.	Yes
B.	No
Answer» C.

Discussion

94.	Dependency notation is no longer used.
A.	1
B.
C.	1
D.
Answer» C. 1

Discussion

95.	Which of the following groups of logic devices would be the minimum required for a MOD-64 synchronous counter?
A.	Five flip-flops, three AND gates
B.	Seven flip-flops, five AND gates
C.	Four flip-flops, ten AND gates
D.	Six flip-flops, four AND gates
Answer» E.

Discussion

96.	Which of the following is an invalid state in an 8421 BCD counter?
A.	11
B.	1001
C.	1000
D.	1100
Answer» E.

Discussion

97.	What is the maximum delay that can occur if four flip-flops are connected as a ripple counter and each flip-flop has propagation delays of tPHL = 22 ns and tPLH = 15 ns?
A.	15 ns
B.	22 ns
C.	60 ns
D.	88 ns
Answer» E.

Discussion

98.	In VHDL, when we want to remember a value it must be stored in a VARIABLE.
A.	1
B.
C.	1
D.
Answer» B.

Discussion

99.	To operate correctly, starting a ring counter requires:
A.	clearing one flip-flop and presetting all the others.
B.	clearing all the flip-flops.
C.	presetting one flip-flop and clearing all the others.
D.	presetting all the flip-flops.
Answer» D. presetting all the flip-flops.

Discussion

100.	The designation means that the ________.
A.	up count is active-HIGH, the down count is active-LOW
B.	up count is active-LOW, the down count is active-HIGH
C.	up and down counts are both active-LOW
D.	up and down counts are both active-HIGH
Answer» B. up count is active-LOW, the down count is active-HIGH

Discussion

Explore topic-wise MCQs in Digital Electronics.

The technique used by one-shots to respond to an edge rather than a level is called ________.

In order to use a shift register as a counter, ________.

Shift-register counters use ________, which means that the output of the last FF in the register is connected back to the first FF in some way.

The minimum number of flip-flops that can be used to construct a modulus-5 counter is ________.

The terminal marked A on the CTR block in the given figure is the SET terminal.

________ is the modulus of the counter shown below.

A glitch is a short pulse resulting in an undesired result in a digital circuit.

All flip-flops in an asynchronous counter change states at the same time.

Many parallel counters use ________ presetting whereby the counter is preset on the active transition of the same clock signal that is used for counting.

In a synchronous counter, each state is clocked by the same pulse.

The serial in/parallel out shift register transfers data from one parallel data bus to another parallel data bus one bit at a time across a single line.

Another term used to describe up/down counters is bidirectional.

An asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be changed to a down counter by ________.

The circuit shown below is a ________.

In a 74192 BCD decade up-/down-counter, the terminal count up and the terminal count down are active-LOW.

Assume a 4-bit ripple counter has a failure in the second flip-flop such that it "locks up." The third and fourth stages will ________.

A reliable method for eliminating decoder spikes is to use strobing.

In general, when using a scope to troubleshoot digital systems the instrument should be triggered by ________.

The given circuit is a(n) ________.

Cascade means to connect the Q output of one flip-flop to the clock input of the next.

In a full-featured counter in HDL, the concept of rolling over simply means the count sequence has reached its limit and must start over at the beginning of the sequence.

A sequential circuit design is used to ________.

A J-K flip-flop is reset and must stay reset after the clock pulse. This transition requires that ________.

The 7447 has a 4-bit BCD input, seven individual active-LOW outputs, and a ripple blanking input and output.

The MOD-10 counter is also referred to as a ________ counter.

A serial in/serial out shift register transfers data from one line of a parallel bus to another line one bit at a time.

The term synchronous refers to events that do not occur at the same time.

The circuit shown below is used for ________, and for the inputs shown, the DATA output will be ________.

Phototransistors have varying resistance from collector to emitter, depending on how much light strikes them.

A D flip-flop can be made to toggle by ________.

The modulus of a counter is the actual number of states in its sequence.

Asynchronous counters are often called ________ counters.

When a J-K flip-flop is used in a circuit, we only have to consider the level at J and K at the active clock edge to know the states of the outputs.

A multiplexed display being driven by a logic circuit:

Any divide-by-N counter can be formed by using external gating to ________ at a predetermined number.

A 4-bit counter has a maximum modulus of ________.

What is the difference between combinational logic and sequential logic?

To design a divide-by-200 counter using synchronous counters, two 4-bit counters could be cascaded together to form an 8-bit counter.

The process of designing a synchronous counter that will count in a nonbinary manner is primarily based on:

A ripple counter's speed is limited by the propagation delay of:

One of the major drawbacks to the use of asynchronous counters is:

Referring to the given figure, at which point is the serial data transferred to the parallel output?

A four-channel scope is used to check the counter in the figure given below. Are the displayed waveforms correct?

Dependency notation is no longer used.

Which of the following groups of logic devices would be the minimum required for a MOD-64 synchronous counter?

Which of the following is an invalid state in an 8421 BCD counter?

What is the maximum delay that can occur if four flip-flops are connected as a ripple counter and each flip-flop has propagation delays of tPHL = 22 ns and tPLH = 15 ns?

In VHDL, when we want to remember a value it must be stored in a VARIABLE.

To operate correctly, starting a ring counter requires:

The designation means that the ________.

The circuit shown below is used for , and for the inputs shown, the DATA output will be .