Explore topic-wise MCQs in Digital Electronics.

This section includes 190 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Electronics knowledge and support exam preparation. Choose a topic below to get started.

101.

In VHDL, if we need to remember a value it must be stored in a ________.

A. function
B. type declaration
C. variable
D. process
Answer» B. type declaration
Discussion
102.

Which is not an example of a truncated modulus?

A. 8
B. 9
C. 11
D. 15
Answer» B. 9
Discussion
103.

Modulus refers to ________.

A. a method used to fabricate decade counter units
B. the modulus of elasticity, or the ability of a circuit to be stretched from one mode to another
C. an input on a counter that is used to set the counter state, such as UP/DOWN
D. the maximum number of states in a counter sequence
Answer» E.
Discussion
104.

What is meant by parallel load of a counter?

A. Each FF is loaded with data on a separate clock.
B. The counter is cleared.
C. All FFs are preset with data.
Answer» D.
Discussion
105.

A state diagram is a table of states.

A. 1
B.
Answer» C.
Discussion
106.

A seven-segment, common-anode LED display is designed for:

A. all cathodes to be wired together
B. one common LED
C. a HIGH to turn off each segment
D. disorientation of segment modules
Answer» D. disorientation of segment modules
Discussion
107.

The final output of a modulus-8 counter occurs one time for every ________.

A. 8 clock pulses
B. 16 clock pulses
C. 24 clock pulses
D. 32 clock pulses
Answer» B. 16 clock pulses
Discussion
108.

In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs?

A. A trigger edge has occurred and we must load the counter.
B. The counter is zero and we need to keep it at zero.
C. The shift register is reset.
D. The counter is not zero and we need to count down by one.
Answer» D. The counter is not zero and we need to count down by one.
Discussion
109.

Which of the following is an example of a counter with a truncated modulus?

A. 8
B. 13
C. 16
D. 32
Answer» C. 16
Discussion
110.

List the state of each output pin of a 7447 if RBI = 0, LT = 1, A0 = 1, A1 = 0, A2 = 0, and A3 = 1.

A. RBO = 0, a = 0, b = 0, c = 0, d = 1, e = 1, f = 0, g = 0
B. RBO = 1, a = 0, b = 0, c = 0, d = 1, e = 1, f = 0, g = 0
C. RBO = 0, a = 0, b = 0, c = 0, d = 0, e = 1, f = 0, g = 0
D. RBO = 1, a = 0, b = 0, c = 0, d = 0, e = 1, f = 0, g = 0
Answer» B. RBO¬†=¬†1, a¬†=¬†0, b¬†=¬†0, c¬†=¬†0, d¬†=¬†1, e¬†=¬†1, f¬†=¬†0, g¬†=¬†0
Discussion
111.

List which pins need to be connected together on a 7492 to make a MOD-12 counter.

A. 1 to 12, 11 to 6, 9 to 7
B. 1 to 12, 12 to 6, 11 to 7
C. 1 to 12, 9 to 6, 8 to 7
D. 1 to 12
Answer» E.
Discussion
112.

Synchronous counters eliminate the delay problems encountered with asynchronous counters because the:

A. input clock pulses are applied only to the first and last stages
B. input clock pulses are applied only to the last stage
C. input clock pulses are not used to activate any of the counter stages
D. input clock pulses are applied simultaneously to each stage
Answer» E.
Discussion
113.

To cascade is to connect in parallel.

A. 1
B.
C. 1
D.
Answer» C. 1
Discussion
114.

Three cascaded decade counters will divide the input frequency by ________.

A. 10
B. 20
C. 100
D. 1000
Answer» E.
Discussion
115.

The parallel outputs of a counter circuit represent the:

A. parallel data word
B. clock frequency
C. counter modulus
D. clock count
Answer» E.
Discussion
116.

In an HDL ring counter, many invalid states are included in the programming by:

A. using a case statement.
B. using an elsif statement.
C. including them under others.
D. the ser_in line.
Answer» D. the ser_in line.
Discussion
117.

What type of register is shown below?

A. Parallel in/parallel out register
B. Serial in/parallel out register
C. Serial/parallel-in parallel-out register
D. Parallel-access shift register
Answer» E.
Discussion
118.

The concept of a counter to implement a digital one-shot using HDL is not used.

A. 1
B.
C. 1
D.
Answer» C. 1
Discussion
119.

A MOD-12 and a MOD-10 counter are cascaded. Determine the output frequency if the input clock frequency is 60 MHz.

A. 500 kHz
B. 1,500 kHz
C. 6 MHz
D. 5 MHz
Answer» B. 1,500 kHz
Discussion
120.

A 12 MHz clock frequency is applied to a cascaded counter containing a modulus-5 counter, a modulus-8 counter, and a modulus-10 counter. The lowest output frequency possible is ________.

A. 10 kHz
B. 20 kHz
C. 30 kHz
D. 60 kHz
Answer» D. 60 kHz
Discussion
121.

A modulus-10 counter must have ________.

A. 10 flip-flops
B. flip-flops
C. 2 flip-flops
D. synchronous clocking
Answer» C. 2 flip-flops
Discussion
122.

In order to check the CLR function of a counter, ________.

A. apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state
B. ground the CLR input and check to be sure that all of the Q outputs are LOW
C. connect the CLR input to Vcc and check to see if all of the Q outputs are HIGH
D. connect the CLR to its correct active level while clocking the counter; check to make sure that all of the Q outputs are toggling
Answer» B. ground the CLR input and check to be sure that all of the Q outputs are LOW
Discussion
123.

What function will the counter shown below be performing during period "B" on the timing diagram?

A. Counting up
B. Counting down
C. Inhibited
D. Loading
Answer» B. Counting down
Discussion
124.

Why can a synchronous counter operate at a higher frequency than a ripple counter?

A. The flip-flops change one after the other.
B. The flip-flops change at the same time.
C. A synchronous counter cannot operate at higher frequencies.
D. A ripple counter is faster.
Answer» C. A synchronous counter cannot operate at higher frequencies.
Discussion
125.

A ripple counter is an asynchronous counter.

A. 1
B.
Answer» B.
Discussion
126.

The terminal count of a typical modulus-10 binary counter is ________.

A. 0
B. 1010
C. 1001
D. 1111
Answer» D. 1111
Discussion
127.

A 22-MHz clock signal is put into a MOD-16 counter. What is the frequency of the Q output of each stage of the counter?

A. Q1 = 22 MHz, Q2 = 11 MHz, Q3 = 5.5 MHz, Q4 = 2.75 MHz
B. Q1 = 11 MHz, Q2 = 5.5 MHz, Q3 = 2.75 MHz, Q4 = 1.375 MHz
C. Q1 = 11 MHz, Q2 = 11 MHz, Q3 = 11 MHz, Q4 = 11 MHz
D. Q1 = 22 MHz, Q2 = 22 MHz, Q3 = 22 MHz, Q4 = 22 MHz
Answer» C. Q1¬†=¬†11 MHz, Q2¬†=¬†11 MHz, Q3¬†=¬†11 MHz, Q4¬†=¬†11 MHz
Discussion
128.

Four cascaded modulus-10 counters have an overall modulus of ________.

A. 10
B. 100
C. 1000
D. 10000
Answer» E.
Discussion
129.

The counter circuit and associated waveforms shown below are for a(n) ________ counter, and the correct output waveform for QB is shown by waveform ________.

A. synchronous, a
B. asynchronous, b
C. synchronous, c
D. asynchronous, d
Answer» D. asynchronous, d
Discussion
130.

A decade counter will count through decimal ________.

A. 10
B. 9
C. 15
D. 0
Answer» C. 15
Discussion
131.

Which segments (by letter) of a seven-segment display need to be active in order to display a digit 6?

A. b, c, d, e, f, and g
B. a, c, d, e, f, and g
C. a, b, c, d, and f
D. b, c, d, e, and f
Answer» C. a, b, c, d, and f
Discussion
132.

In many cases, counters must be strobed in order to eliminate glitches.

A. 1
B.
Answer» B.
Discussion
133.

What is the difference between a 7490 and a 7493?

A. 7490 is a MOD-10, 7493 is a MOD-16
B. 7490 is a MOD-16, 7493 is a MOD-10
C. 7490 is a MOD-12, 7493 is a MOD-16
D. 7490 is a MOD-10, 7493 is a MOD-12
Answer» B. 7490 is a MOD-16, 7493 is a MOD-10
Discussion
134.

Which of the following is a type of shift register counter?

A. Decade
B. Binary
C. Ring
D. BCD
Answer» D. BCD
Discussion
135.

How many different states does a 2-bit asynchronous counter have?

A. 1
B. 2
C. 4
D. 8
Answer» D. 8
Discussion
136.

A glitch that appears on the decoded output of a ripple counter is often difficult to see on an oscilloscope because ________.

A. it is a random event
B. it occurs less frequently than the normal decoded output
C. it is very fast
D. all of the above
Answer» E.
Discussion
137.

Once an up-/down-counter begins its count sequence, it cannot be reversed.

A. 1
B.
Answer» C.
Discussion
138.

The circuit given below fails to produce data output. The individual flip-flops are checked with a logic probe and pulser, and each checks OK. What could be causing the problem?

A. The data output line may be grounded.
B. One of the clock input lines may be open.
C. One of the interconnect lines between two stages may have a solder bridge to ground.
D. One of the flip-flops may have a solder bridge between its input and Vcc.
Answer» C. One of the interconnect lines between two stages may have a solder bridge to ground.
Discussion
139.

After 10 clock cycles, and assuming that the DATA input had returned to 0 following the storage sequence, what values would be stored in Q4, Q3, Q2, Q1, Q0 of the register in Figure 7-5?

A. 0,1,0,1,1
B. 1,1,0,1,0
C. 1,0,1,0,1
D. 0,0,0,0,0
Answer» E.
Discussion
140.

Three cascaded modulus-10 counters have an overall modulus of 1000.

A. 1
B.
C. 1
D.
Answer» B.
Discussion
141.

How many AND gates would be required to completely decode ALL the states of a MOD-64 counter, and how many inputs must each AND gate have?

A. 128 gates, 6 inputs to each gate
B. 64 gates, 5 inputs to each gate
C. 64 gates, 6 inputs to each gate
D. 128 gates, 5 inputs to each gate
Answer» D. 128 gates, 5 inputs to each gate
Discussion
142.

An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required?

A. None
B. One
C. Two
D. Fifteen
Answer» E.
Discussion
143.

A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(tot)) is ________.

A. 12 ms
B. 24 ns
C. 48 ns
D. 60 ns
Answer» E.
Discussion
144.

A(n) ________ one-shot starts a pulse in response to a trigger and will restart the internal pulse timer every time a subsequent trigger edge occurs before the pulse is complete.

A. non-retriggerable
B. retriggerable
C. high-level triggered
D. edge-triggered
Answer» C. high-level triggered
Discussion
145.

Counters are generally decoded in order to determine their count state.

A. 1
B.
C. 1
D.
Answer» B.
Discussion
146.

How many flip-flops are required to construct a decade counter?

A. 10
B. 8
C. 5
D. 4
Answer» E.
Discussion
147.

For a multistage counter to be truly synchronous, the ________ of each stage must be connected to ________.

A. Cp, the same clock input line
B. CE, the same clock input line
C. , the terminal count output
D. , both clock input lines
Answer» B. CE, the same clock input line
Discussion
148.

The terminal count of a 3-bit binary counter in the DOWN mode is ________.

A. 0
B. 111
C. 101
D. 10
Answer» B. 111
Discussion
149.

Which of the following is an invalid output state for an 8421 BCD counter?

A. 1110
B. 0
C. 10
D. 1
Answer» B. 0
Discussion
150.

A BCD counter has ________ states.

A. 8
B. 9
C. 10
D. 11
Answer» D. 11
Discussion