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MCQOPTIONS
This section includes 249 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Electronics knowledge and support exam preparation. Choose a topic below to get started.
| 51. |
Consider the two cascaded 2-to-1 multiplexers as shown in the figure.The minimal sum of products form of the output X is |
| A. | P̅ Q̅ + PQR |
| B. | P̅ Q + QR |
| C. | PQ + P̅ Q̅ R |
| D. | Q̅ R̅ + PQR |
| Answer» E. | |
| 52. |
If a, b, c are 3-input variables, then Boolean function y = ab + bc + ca represents1. A 3-input majority gate2. A 3-input minority gate3. Carry output of a full adder4. Product circuit for a, b and cWhich of the above statements are correct? |
| A. | 2 and 3 |
| B. | 2 and 4 |
| C. | 1 and 3 |
| D. | 1 and 4 |
| Answer» D. 1 and 4 | |
| 53. |
How many 4 to 1 multiplexers are required to implement 16 to 1 multiplexer? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» E. | |
| 54. |
_____ data transmission is more useful when sending information for long distances |
| A. | Serial |
| B. | Parallel |
| C. | Either |
| D. | Neither |
| Answer» B. Parallel | |
| 55. |
Find the number of 2 × 1 MUX (multiplexers) required to implement 16 × 1 MUX. |
| A. | 15 |
| B. | 20 |
| C. | 5 |
| D. | 9 |
| Answer» B. 20 | |
| 56. |
In a multiplexer, if there are 4 input lines and 1 output line, then number of selection lines will be: |
| A. | 3 |
| B. | 0 |
| C. | 2 |
| D. | 1 |
| Answer» D. 1 | |
| 57. |
In the above circuit, X is given by: |
| A. | \(X = A {\bar B \bar C} + \overline A B\overline C + {\bar A \bar B}{C} + ABC\) |
| B. | \(X = \overline A BC + A\overline B C + AB\overline C + \overline {ABC} \) |
| C. | X = AB + BC + AC |
| D. | \(X = \overline {AB} + \overline {BC} + \overline {AC} \) |
| Answer» B. \(X = \overline A BC + A\overline B C + AB\overline C + \overline {ABC} \) | |
| 58. |
Half adder is a logic circuit that accepts ________ single bit inputs. |
| A. | Three |
| B. | Two |
| C. | Four |
| D. | Five |
| Answer» C. Four | |
| 59. |
A 3 to 8 Decoder is shown in the figure. Find F(x2; x1; x0) |
| A. | F = ∑ m (1, 4, 7) |
| B. | F = ∑m (0, 2, 3, 5, 6) |
| C. | F = x0 + x1 + x2 |
| D. | \(F = \overline {x0 + x1 + x2} \) |
| Answer» C. F = x0 + x1 + x2 | |
| 60. |
Boolean expression for the output of the logic circuit shown in the figure is |
| A. | \(Y = AB + AB + C\) |
| B. | \(Y = \overline A \overline B + AB + \overline C \) |
| C. | \(Y\, = \,A\overline B \, + \,\overline A B\, + C\) |
| D. | \(Y\, = \,AB\, + \,\overline A B\, + C\) |
| Answer» C. \(Y\, = \,A\overline B \, + \,\overline A B\, + C\) | |
| 61. |
A binary-to-BCD encoder has four inputs D0 C0, B0, and A0 and five outputs D, C, B, A, and VALID. The outputs D, C, B and A give the proper BCD value of the input and the VALID output is 1 if the input combination is a valid decimal code. If the input combination is an invalid decimal code, the VLID output becomes 0, and all of the D, C, B, and A outputs show 0 values. If only NOT gates and 2-input OR and AND gates are available, the minimum number of gates required to implement the above circuit is |
| A. | 10 |
| B. | 9 |
| C. | 8 |
| D. | 7 |
| Answer» D. 7 | |
| 62. |
In a half-subtractor circuit with X and Y as inputs, the Borrow (M) and Difference (N = X - Y) are given by |
| A. | M = X ⊕ Y, N = XY |
| B. | M = XY, N = X ⊕ Y |
| C. | M = X̅Y, N = X ⊕ Y |
| D. | M = XY̅, \(N = \overline {X \oplus Y} \) |
| Answer» D. M = XY̅, \(N = \overline {X \oplus Y} \) | |
| 63. |
A 4 × 1 Multiplexer is shown in the Figure below. The output Z is |
| A. | A NOR C |
| B. | B NOR C |
| C. | B XOR C |
| D. | A XOR C |
| Answer» E. | |
| 64. |
Identify the circuit below. |
| A. | Binary to Gray code converter |
| B. | Binary to XS3 converter |
| C. | Gray to Binary converter |
| D. | XS3 to Binary converter |
| Answer» D. XS3 to Binary converter | |
| 65. |
Consider the following statements :1. An 8-input MUX can be used to implement any 4 variable functions.2. A 3-line to 8-line DEMUX can be used to implement any 4 variable functions.3. A 64-input MUX can be built using nine 8-input MUXs.4. A 6-line to 64-line DEMUX can be built using nine 3-line to 8-line DEMUXs.Which of the above statements are correct ? |
| A. | 1, 2, 3 and 4 |
| B. | 1, 2 and 4 only |
| C. | 3 and 4 only |
| D. | 1, 2 and 3 only |
| Answer» D. 1, 2 and 3 only | |
| 66. |
A Boolean function f(A,B,C,D) = \(\mathop \prod \nolimits \left( {1,5,12,15} \right)\) is to be implemented using an 8×1 multiplexer (A is MSB). The inputs ABC are connected to the select inputs S2S1S0 of the multiplexer respectively.Which one of the following options gives the correct inputs to pins 0, 1, 2, 3, 4, 5, 6, 7 in order? |
| A. | D, 0, D, 0, 0, 0, D’, D |
| B. | D’, 1, D’, 1, 1, 1, D, D’ |
| C. | D, 1, D, 1, 1, 1, D’, D |
| D. | D’, 0, D’, 0, 0, 0, D, D’ |
| Answer» C. D, 1, D, 1, 1, 1, D’, D | |
| 67. |
A 4-bit XS-3 parallel adder needs ______ 4-bit parallel adder IC 74LS83s. |
| A. | 3 |
| B. | 2 |
| C. | 4 |
| D. | 1 |
| Answer» C. 4 | |
| 68. |
A multiplexer is a |
| A. | combinational circuit |
| B. | flip-flop |
| C. | sequential circuit |
| D. | comparator |
| Answer» B. flip-flop | |
| 69. |
Assertion (A) : A multiplexer (MUX) is a device which selects one of the many inputs to a single output.Reason (R): A digital multiplexer is a sequential circuit that selects binary information from one of the many input line sand directs it to a single output line |
| A. | Both (A) and (R) are true and (R) is the correct explanation of (A) |
| B. | Both (A) and (R) are true, but (R) is not the correct explanation of (A) |
| C. | (A) is true, but (R) is false |
| D. | (A) false, but (R) is true |
| Answer» D. (A) false, but (R) is true | |
| 70. |
Match the following. List - 1 List – 2I.RegisterA.Sequential circuitII.DecoderB.XYIII.X + XYC.Combinational circuitIV.X(X’ + Y)D.X |
| A. | I – A, II – C, III – D, IV - B |
| B. | I – C, II – A, III – D, IV - B |
| C. | I – A, II – C, III – B, IV - D |
| D. | I – C, II – A, III – B, IV - D |
| Answer» B. I – C, II – A, III – D, IV - B | |
| 71. |
Half adder has |
| A. | Two inputs and one output |
| B. | Two inputs and two outputs |
| C. | Three inputs and two outputs |
| D. | Three inputs and one output |
| Answer» C. Three inputs and two outputs | |
| 72. |
If half adders and full adders are implements using gates, then for the addition of two 17 bit numbers (using minimum gates) the number of half adders and full adders required will be |
| A. | 0, 17 |
| B. | 16, 1 |
| C. | 1, 16 |
| D. | 8, 8 |
| Answer» D. 8, 8 | |
| 73. |
Directions: The item consists of two statements, one labelled as the ‘Assertion (A)’ and the other as ‘Reason (R)’.You are to examine these two statements carefully and select the answers to the item using the codes given below:Assertion (A): The TTL NAND gate in tristate output configuration can be used for a bus arrangement with more than one gate output connected to a common line.Reason (R): The tristate configuration has a control input, which can detach a logic level (0/1) from coming onto the bus line. |
| A. | Both A and R individually true and R is the correct explanation of A |
| B. | Both A and R are individually true but R is not the correct explanation of A |
| C. | A is true but R is false |
| D. | A is false but R is true |
| Answer» B. Both A and R are individually true but R is not the correct explanation of A | |
| 74. |
A 4 × 1 multiplexer with two selector lines is used to realize a Boolean function F having four Boolean variables X, Y, Z and W as shown below. S0 and S1 denote the least significant bit (LSB) and most significant bit (MSB) of the selector lines of the multiplexer respectively. I0, I1, I2, I3 are the input lines of the multiplexer.The canonical sum of product representation of F is |
| A. | F (X, Y, Z, W) = Σ m(0 , 1, 3, 14, 15) |
| B. | F (X, Y, Z, W) = Σ m( 0, 1, 3,11,14) |
| C. | F (X, Y, Z, W) = Σ m( 2, 5, 9, 11, 14) |
| D. | F (X, Y, Z, W) = Σ m(1,3,7,9,15) |
| Answer» C. F (X, Y, Z, W) = Σ m( 2, 5, 9, 11, 14) | |
| 75. |
Consider the following statements with respect to the combinational circuit:1. The output at any time depends only on the present combination of inputs.2. It does not employ storage elements.3. It performs an operation that can be specified logically by a set of Boolean functions.Which of the above statements are correct? |
| A. | 1 and 2 only |
| B. | 1 and 3 only |
| C. | 2 and 3 only |
| D. | 1, 2 and 3 |
| Answer» E. | |
| 76. |
How many 3 to 8 line decoders with an enabler input are needed to construct a 6 to 64 line decoder without using any other logic gates? |
| A. | 11 |
| B. | 10 |
| C. | 9 |
| D. | 8 |
| Answer» D. 8 | |
| 77. |
Consider the logic circuit with input signal TEST shown in the figure. All gates in the figure shown have identical non-zero delay. The signal TEST which was at logic LOW is switched to logicHIGH and maintained at logic HIGH. The output |
| A. | stays HIGH throughout |
| B. | stays LOW throughout |
| C. | pulses from LOW to HIGH to LOW |
| D. | pulses from HIGH to LOW to HIGH |
| Answer» E. | |
| 78. |
A sequence detector is designed to detect precisely 3 digital inputs, with overlapping sequences detectable. For the sequence (1,0,1) and input data (1,1,0,1,0,0,1,1,0,1,0,1,1,0), what is the output of this detector? |
| A. | 1,1,0,0,0,0,1,1,0,1,0,0 |
| B. | 0,1,0,0,0,0,0,1,0,1,0,0 |
| C. | 0,1,0,0,0,0,0,1,0,1,1,0 |
| D. | 0,1,0,0,0,0,0,0,1,0,0,0 |
| Answer» C. 0,1,0,0,0,0,0,1,0,1,1,0 | |
| 79. |
A logic circuit that accepts several data inputs and allows only one of them at a time to get through to the output is called |
| A. | Multiplexer |
| B. | De-multiplexer |
| C. | Transmitter |
| D. | Receiver |
| Answer» B. De-multiplexer | |
| 80. |
For realizing a binary half-subtractor having two inputs A and B, the current set of logical expression for the outputs D (A minus B) and X (borrow) are1. The difference output D = A̅B + AB̅2. The borrow output B = AB̅Which of the above statements is/are correct? |
| A. | 1 only |
| B. | 2 only |
| C. | Both 1 and 2 |
| D. | Neither 1 nor 2 |
| Answer» B. 2 only | |
| 81. |
Depth of an Arithmetic Circuit is |
| A. | Number of Gates in it |
| B. | Length of the longest path in it |
| C. | Sum of Number of Gates and Length |
| D. | None of these |
| Answer» C. Sum of Number of Gates and Length | |
| 82. |
Identify the IC-74147. |
| A. | BCD to Decimal Decoder |
| B. | Octal to Binary priority Encoder |
| C. | Decimal to BCD priority Encoder |
| D. | BCD to 7-Segment Decoder |
| Answer» D. BCD to 7-Segment Decoder | |
| 83. |
In a combinational circuit, which of the following is used to send more data through a single transmission? |
| A. | Encoder |
| B. | Demultiplexer |
| C. | Multiplexer |
| D. | Decoder |
| Answer» D. Decoder | |
| 84. |
Number of control lines required for 16 to 1 multiplexer is _____ |
| A. | 3 |
| B. | 4 |
| C. | 8 |
| D. | 2 |
| Answer» C. 8 | |
| 85. |
A binary full-subtractor: |
| A. | consists of two cascaded half-subtractors |
| B. | contains two half-subtractors and one OR gate |
| C. | can subtract any binary number |
| D. | can be made out of a full-adder |
| Answer» C. can subtract any binary number | |
| 86. |
Directions: The following items consist of two statements, one labeled as the ‘Statement (I)’ and the other as ‘Statement (II)’. Examine these two statements carefully and select the answers to these items using the codes given below:Statement (I): A NAND gate represents a universal logic family.Statement (II): Only two NAND gates are sufficient to accomplish any of the basic gates.Codes: |
| A. | Both Statement (I) and Statement (II) are individually true and Statement (II) is the correct explanation of Statement (I). |
| B. | Both Statement (I) and Statement (II) are individually true but Statement (II) is mot the correct explanation of Statement (I). |
| C. | Statement (I) is true but Statement (II) is false. |
| D. | Statement (I) is false but Statement (II) is true. |
| Answer» D. Statement (I) is false but Statement (II) is true. | |
| 87. |
Consider the following statements :A multiplexer1. selects one of the several inputs and transmits it to a single output.2. routes the data from a single input to one of many outputs.3. converts parallel data into serial data.4. is a combinational circuit.Which of the above statements are correct? |
| A. | 1 and 3 only |
| B. | 2 and 4 only |
| C. | 1, 3 and 4 only |
| D. | 2, 3 and 4 only |
| Answer» D. 2, 3 and 4 only | |
| 88. |
In given Combination logic, X is given by |
| A. | X = AB̅C̅ + A̅BC̅ + A̅B̅C + ABC |
| B. | X = A̅BC + AB̅C + ABC̅ + A̅B̅C̅ |
| C. | X = AB + BC + AC |
| D. | X = A̅B̅ + B̅C̅ + A̅C̅ |
| Answer» B. X = A̅BC + AB̅C + ABC̅ + A̅B̅C̅ | |
| 89. |
A 4 bit Digital to Analog converter (DAC) gives an output voltage of 5 V for an input code of 1111. What is the output voltage for an input code of 1100? |
| A. | 1 V |
| B. | 2 V |
| C. | 3 V |
| D. | 4 V |
| Answer» E. | |
| 90. |
In a 8-bit ripple carry adder using identical full adders, each full adder takes 34 ns for computing sum. If the time taken for 8-bit addition is 90 ns, find time taken by each full adder to find carry |
| A. | 6 ns |
| B. | 7 ns |
| C. | 10 ns |
| D. | 8 ns |
| Answer» E. | |
| 91. |
Logic Half adder can be made using |
| A. | Two inputs and two outputs |
| B. | Three inputs and two outputs |
| C. | Two inputs and one output |
| D. | Three inputs and one output |
| Answer» B. Three inputs and two outputs | |
| 92. |
A 4:1 multiplexer is to be used for generating the output carry of a full adder. A and B are the bits to be added while Cin is the input carry and Cout is the output carry. A and B are to be used as the select bits with A being the more significant select bit. |
| A. | I0 = 0, I1 = Cin, I2 = Cin and I3 = 1 |
| B. | I0 = 1, I1 = Cin, I2 = Cin and I3 = 1 |
| C. | I0 = Cin, I1 = 0, I2 = 1 and I3 = Cin |
| D. | I0 = 1, I1 = Cin, I2 = 1 and I3 = Cin |
| Answer» B. I0 = 1, I1 = Cin, I2 = Cin and I3 = 1 | |
| 93. |
Identify the gate realized by the MOSFET circuit shown below |
| A. | AND gate |
| B. | NAND gate |
| C. | OR gate |
| D. | NOR gate |
| Answer» C. OR gate | |
| 94. |
A single Decimal-to-BCD encoder has _______ outputs. |
| A. | 4 |
| B. | 10 |
| C. | 8 |
| D. | 5 |
| Answer» B. 10 | |
| 95. |
Based on the paragraph given below answer the following question:The traditional methods of combinational circuits involve simplification and realization using gates. Using these methods, complex functions have been integrated and are easily available in IC form. There is an attractive array of devices like a multiplexer, demultiplexer, decoders, comparators, parity generators/checkers, which significantly reduce IC package count there by reducing the system cost. The system design is greatly simplified because the laborious and time-consuming simplification methods are generally not required with these devices. This also improves the reliability of the system by reducing the number of external wired connections. But they have some limitations as well. Different memories like ROM, PROM can also be used to implement combinational circuits without much simplification.The minimum number of selection lines required for selecting one of the 16 inputs are: |
| A. | 4 |
| B. | 2 |
| C. | 8 |
| D. | 16 |
| Answer» B. 2 | |
| 96. |
A 2-bit full adder circuit may be designed with the help of the following 2-input logic gates. |
| A. | 2-XOR, 2-AND, 1-OR |
| B. | 2-NOR, 2-NAND |
| C. | 1-XOR, 1-AND, 1-OR |
| D. | 2-AND, 2-OR |
| Answer» B. 2-NOR, 2-NAND | |
| 97. |
Consider the logic circuit given below:Q = ______ ? |
| A. | A̅C + BC̅ + CD |
| B. | ABC + C̅D |
| C. | AB + BC̅ + BD̅ |
| D. | AB̅ + AC̅ + C̅D |
| Answer» D. AB̅ + AC̅ + C̅D | |
| 98. |
In full adder, there are |
| A. | Two binary number inputs and two outputs |
| B. | Three binary digit inputs and two binary digit outputs |
| C. | Three binary digit inputs and three binary digit outputs |
| D. | NAND and OR gates |
| Answer» C. Three binary digit inputs and three binary digit outputs | |
| 99. |
A digital multiplexer can be used for which if the following?1. Parallel to serial conversion2. Many to one switch3. To generate memory chip select4. For code conversionSelect the correct answer using the code given below – |
| A. | 1, 3 and 4 |
| B. | 2, 3 and 4 |
| C. | 1 and 2 only |
| D. | 2 and 3 only |
| Answer» D. 2 and 3 only | |
| 100. |
Assuming that only logic inputs X and Y are available and their complements X̅ and Y̅ are not available, the minimum number of two-input NAND gates required to implement X ⊕ Y would be |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» D. 5 | |