MCQOPTIONS
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MCQOPTIONS
This section includes 157 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Electronics knowledge and support exam preparation. Choose a topic below to get started.
| 101. |
What programmable technology is used in FPGA devices? |
| A. | SRAM |
| B. | FLASH |
| C. | Antifuse |
| D. | All of the above |
| Answer» E. | |
| 102. |
The ________ is the most popular standard logic device family today. |
| A. | TTL |
| B. | CMOS |
| C. | ECL |
| D. | None of the above |
| Answer» C. ECL | |
| 103. |
The content of a simple programmable logic device (PLD) consists of: |
| A. | fuse-link arrays |
| B. | thousands of basic logic gates |
| C. | advanced sequential logic functions |
| D. | thousands of basic logic gates and advanced sequential logic functions |
| Answer» E. | |
| 104. |
SPLD is a program language used by PLD software. |
| A. | 1 |
| B. | |
| C. | 1 |
| D. | |
| Answer» C. 1 | |
| 105. |
Why have PLDs taken over so much of the market? |
| A. | One PLD does the work of many ICs. |
| B. | The PLDs are cheaper. |
| C. | Less power is required. |
| D. | All of the above |
| Answer» E. | |
| 106. |
The output of this circuit is always ________. |
| A. | 1 |
| B. | 0   |
| C. | A |
| D. | A |
| Answer» D. A | |
| 107. |
A slice consists of ________. |
| A. | only two logic cells |
| B. | between 2 and 8 logic cells |
| C. | up to 16 logic cells |
| D. | a single CLB |
| Answer» B. between 2 and 8 logic cells | |
| 108. |
The Altera FLEX10K family uses a look-up table (LUT) architecture. |
| A. | 1 |
| B. | |
| C. | 1 |
| D. | |
| Answer» B. | |
| 109. |
Each programmable array logic (PAL) gate product is applied to an OR gate and, if combinational logic is desired, the product is ORed and then: |
| A. | the polarity fuse is restored |
| B. | sent to an inverter for output |
| C. | sent immediately to an output pin |
| D. | passed to the AND function for output |
| Answer» C. sent immediately to an output pin | |
| 110. |
A macrocell basically contains ________. |
| A. | a programmable AND-OR gate array and some input buffers |
| B. | an OR-gate array and some output logic |
| C. | an AND-OR gate array and some output logic |
| D. | licensed programming |
| Answer» C. an AND-OR gate array and some output logic | |
| 111. |
The complex programmable logic device (CPLD) contains several PAL-type simple programmable logic devices (SPLDs) called: |
| A. | macrocells |
| B. | microcells |
| C. | AND/OR arrays |
| D. | fuse-link arrays |
| Answer» B. microcells | |
| 112. |
How many product terms can a MAX+Plus II compiler borrow from adjacent macrocells in the same LAB? |
| A. | 0 |
| B. | 5 |
| C. | 10 |
| D. | 20 |
| Answer» C. 10 | |
| 113. |
Using a hardware solution for a digital system is always ________ than a software solution. |
| A. | slower |
| B. | harder |
| C. | easier |
| D. | faster |
| Answer» E. | |
| 114. |
In an OLMC, where does the FMUX signal go? |
| A. | OMUX |
| B. | D flip-flop |
| C. | Matrix |
| D. | PAL |
| Answer» D. PAL | |
| 115. |
In the MAX7000S device up to ________ signals can feed each LAB from the PIA. |
| A. | 0 |
| B. | 18 |
| C. | 36 |
| D. | 72 |
| Answer» D. 72 | |
| 116. |
What is an OTP device? |
| A. | Optical transporting port |
| B. | Octal transmitting pixel |
| C. | Operational topical portable |
| D. | One-time programmable |
| Answer» E. | |
| 117. |
Which is not a type of PLD? |
| A. | SPLD |
| B. | HPLD |
| C. | CPLD |
| D. | FPGA |
| Answer» C. CPLD | |
| 118. |
A(n) ________ is a section of embedded logic that is commonly found in FPGAs. |
| A. | LUT |
| B. | core |
| C. | DSP |
| D. | PI |
| Answer» C. DSP | |
| 119. |
What is the defining difference between microprocessor/DSP systems and other digital systems? |
| A. | The digital system follows a programmed sequence of instructions that the designer specified. |
| B. | The microprocessor follows a programmed sequence of instructions that the designer specified. |
| C. | The digital system is faster. |
| D. | The microprocessor/DSP is faster. |
| Answer» B. The microprocessor follows a programmed sequence of instructions that the designer specified. | |
| 120. |
By adding an OR gate to a simple programmable logic device (SPLD) the foundation for a(n) ________ is made possible. |
| A. | PAL |
| B. | PLA |
| C. | CPLD |
| D. | EEPROM |
| Answer» B. PLA | |
| 121. |
The Boolean expression (A + B)(C + D) is an example of ________. |
| A. | LAB |
| B. | LUT |
| C. | SOP |
| D. | POS |
| Answer» E. | |
| 122. |
Cascade chains are closely associated with ________. |
| A. | CLBs |
| B. | SOP functions |
| C. | logic expansion |
| D. | all of the above |
| Answer» E. | |
| 123. |
The schematic editor allows you to connect with predefined logic symbols. |
| A. | 1 |
| B. | |
| C. | 1 |
| D. | |
| Answer» B. | |
| 124. |
An SPLD listed as 16H8 would have ________. |
| A. | active-HIGH outputs |
| B. | active-LOW outputs |
| C. | variable-level outputs |
| D. | latches at the outputs |
| Answer» B. active-LOW outputs | |
| 125. |
Generally, PLDs can be described as being one of four different types. |
| A. | 1 |
| B. | |
| Answer» C. | |
| 126. |
What is the status of a tristate output buffer on a MAX7000S family device? |
| A. | It is permanently enabled or disabled. |
| B. | It is controlled by one of the two global output enable pins. |
| C. | It is controlled by other inputs or functions generated by other macrocells. |
| D. | All of the above |
| Answer» E. | |
| 127. |
In the GAL16V8, the ________ controls the tristate buffer's enable input. |
| A. | FMUX |
| B. | OMUX |
| C. | PTMUX |
| D. | TMUX |
| Answer» E. | |
| 128. |
Which of the following testing procedures uses the JTAG IEEE standard? |
| A. | Bed-of-nails |
| B. | Flying probe |
| C. | EXTEST |
| D. | Boundary scan |
| Answer» E. | |
| 129. |
LUT is an acronym for look-up table. |
| A. | 1 |
| B. | |
| C. | 1 |
| D. | |
| Answer» B. | |
| 130. |
In a FLEX10K device, the carry chain provides a fast carry forward function between ________. |
| A. | LUTs |
| B. | EABs |
| C. | LEs |
| D. | LABs |
| Answer» D. LABs | |
| 131. |
Which of the following increases the number of product terms by borrowing unused product from other macrocells? |
| A. | Shared expander |
| B. | Parallel expander |
| C. | Series expander |
| D. | Slice expander |
| Answer» C. Series expander | |
| 132. |
The programming technologies that are used in FPGA devices include SRAM, flash, and antifuse, with flash being most common. |
| A. | 1 |
| B. | |
| Answer» C. | |
| 133. |
In a FLEX10K, what two outputs will the LE produce? |
| A. | The LAB and the fast track |
| B. | ON and OFF |
| C. | Hi-Z and ON |
| D. | Hi-Z and OFF |
| Answer» B. ON and OFF | |
| 134. |
The field programmable logic array was the first ________ programmable logic device. |
| A. | understandable |
| B. | logic array |
| C. | multifunction |
| D. | nonmemory |
| Answer» E. | |
| 135. |
When did the first PLD appear? |
| A. | More than 10 years ago |
| B. | More than 20 years ago |
| C. | More than 30 years ago |
| D. | More than 40 years ago |
| Answer» D. More than 40 years ago | |
| 136. |
What can the GAL22V10 do that the GAL16V8 cannot? |
| A. | It has an extra-large array. |
| B. | It is in-system programmable. |
| C. | It has twice the special function pins. |
| D. | All of the above |
| Answer» C. It has twice the special function pins. | |
| 137. |
What is PROM? |
| A. | SPLD |
| B. | QPLD |
| C. | HPLD |
| D. | PLD |
| Answer» E. | |
| 138. |
Product terms are the outputs of which type of gate within a PLD array? |
| A. | OR |
| B. | XOR |
| C. | AND |
| D. | flip-flop |
| Answer» D. flip-flop | |
| 139. |
What is an EPM7128S? |
| A. | An Altera MAX7000S CPLD |
| B. | An Altera UP2 |
| C. | A DeVry eSOC |
| D. | A BSR PL DT-2 |
| Answer» B. An Altera UP2 | |
| 140. |
A look-up table is simply a truth table with all the possible output connections listed with their desired input response. |
| A. | 1 |
| B. | |
| C. | compiling |
| D. | downloading |
| Answer» C. compiling | |
| 141. |
Which is a mode of operation of the GAL16V8? |
| A. | Simple mode |
| B. | Complex mode |
| C. | Registered mode |
| D. | All of the above |
| Answer» E. | |
| 142. |
A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmer interconnect that is used to connect internal logic modules is called a ________. |
| A. | bed-of-nails |
| B. | boundary scan |
| C. | CLB |
| D. | CPLD |
| Answer» D. CPLD | |
| 143. |
FPLA is: |
| A. | a nonmemory programmable device. |
| B. | a programmable AND array. |
| C. | a programmable OR array. |
| D. | All of the above |
| Answer» E. | |
| 144. |
ALM is the acronym for ________. |
| A. | Array Logic Matrix |
| B. | Arithmetic Logic Module |
| C. | Asynchronous Local Modulator |
| D. | Adaptive Logic Module |
| Answer» E. | |
| 145. |
Field-programmable gate arrays (FGPAs) use ________ memory technology, which is ________. |
| A. | DRAM, nonvolatile |
| B. | SRAM, nonvolatile |
| C. | SRAM, volatile |
| D. | RAM, volatile |
| Answer» D. RAM, volatile | |
| 146. |
The GAL16V8 has: |
| A. | 16 dedicated inputs. |
| B. | 8 special function pins. |
| C. | 8 pins that are used as inputs or outputs. |
| D. | All of the above |
| Answer» D. All of the above | |
| 147. |
What is the input/output pin configuration of the GAL22V10? |
| A. | 10 output pins and 12 input pins |
| B. | 2 special-purpose pins |
| C. | 8 pins that are either inputs or outputs |
| D. | All of the above |
| Answer» B. 2 special-purpose pins | |
| 148. |
How many pins are in an EDF10K70 package? |
| A. | 70 |
| B. | 140 |
| C. | 240 |
| D. | 532 |
| Answer» D. 532 | |
| 149. |
Which is not a part of a GAL16V8's OLMC? |
| A. | TSMUX |
| B. | OMUX |
| C. | FMUX |
| D. | PSMUX |
| Answer» E. | |
| 150. |
A(n) ________ consists of a programmable array of AND gates that connects to a fixed array of OR gates and is usually OTP. |
| A. | GAL |
| B. | CPLD |
| C. | PAL |
| D. | SPLD |
| Answer» D. SPLD | |