157 + Mcqs in Programmable Logic Device Page 2 McqOptions

51.	Xilinx software uses triangular symbols called buffers to define pins as input or output.
A.	1
B.
Answer» C.

Discussion

52.	In a MAX7000S device, when an I/O pin is configured as an input, the associated macrocell can be used for ________.
A.	buried logic
B.	another output
C.	extra speed
D.	in-system testing
Answer» B. another output

Discussion

53.	The GAL16V8 has 32 input variables.
A.	1
B.
Answer» B.

Discussion

54.	A complex programmable logic device that consists of multiple SPLD arrays with programmable interconnections is called a ________.
A.	bed-of-nails
B.	boundary scan
C.	CLB
D.	CPLD
Answer» E.

Discussion

55.	The major structures of the MAX7000S are the logic array block (LAB) and the programmable intermediate array (PIA).
A.	1
B.
Answer» C.

Discussion

56.	In the GAL16V8, the ________ selects the signal that is fed back into the input matrix.
A.	FMUX
B.	OMUX
C.	PTMUX
D.	TSMUX
Answer» B. OMUX

Discussion

57.	An expensive form of programmable logic is SPLD.
A.	1
B.
Answer» C.

Discussion

58.	Most PAL devices have a tristate buffer driving the input pins.
A.	1
B.
Answer» C.

Discussion

59.	The programming technologies that are used in FPGA devices include SRAM, flash, and antifuse, with ________ being the most common.
A.	SRAM
B.	flash
C.	antifuse
D.	SRAM and flash
Answer» B. flash

Discussion

60.	With microcomputer/DSP systems, devices can be electronically controlled and data can be manipulated by executing a program of instructions that has been written for the application.
A.	1
B.
Answer» B.

Discussion

61.	Most complex digital designs include ________.
A.	standard logic devices
B.	ASIC devices
C.	microprocessor/DSP devices
D.	a mix of different hardware categories
Answer» E.

Discussion

62.	A method for the automated testing of printed circuit boards is called a(n) ________.
A.	bed-of-nails
B.	LUT
C.	CLB
D.	CPLD
Answer» B. LUT

Discussion

63.	The PAL structure is able to perform any sum-of-products (SOP) operation.
A.	1
B.
Answer» B.

Discussion

64.	The Boolean expression AB + CD is an example of ________.
A.	PAL
B.	GAL
C.	SOP
D.	POS
Answer» D. POS

Discussion

65.	The PAL has an AND and OR structure similar to a PROM, but in the PAL the inputs to the AND gates are programmable, whereas the inputs to the OR gate are hard-wired.
A.	1
B.
C.	1
D.
Answer» B.

Discussion

66.	What is the major downfall of microprocessor/DSP systems?
A.	Speed‚Äîthey are too fast
B.	Speed‚Äîthey are too slow
C.	Too much flexibility
D.	Not enough flexibility
Answer» C. Too much flexibility

Discussion

67.	An SPLD listed as 22V10 has ________.
A.	10 inputs, 10 outputs, and requires a 22 V power source
B.	11 inputs, 11 outputs, and requires a 10 V power source
C.	22 inputs and 10 outputs
D.	10 inputs and 22 outputs
Answer» D. 10 inputs and 22 outputs

Discussion

68.	What is another name for digital circuitry called sequential logic?
A.	logic macrocell
B.	logic array
C.	flip-flop memory circuitry
D.	inverter
Answer» D. inverter

Discussion

69.	A GAL22V10 ________.
A.	has up to 32 inputs and 10 outputs
B.	is a type of SPLD
C.	has 10 inputs and 22 outputs
D.	is downloadable from the manufacturer's Web site
Answer» C. has 10 inputs and 22 outputs

Discussion

70.	Which of the following testing procedures has one or more external moving parts?
A.	Bed-of-nails
B.	Flying probe
C.	EXTEST
D.	Boundary scan
Answer» C. EXTEST

Discussion

71.	PLDs did not gain widespread acceptance with digital until the mid-1980s, when a device called a PAL was introduced.
A.	1
B.
C.	1
D.
Answer» C. 1

Discussion

72.	Most look-up tables in field-programmable gate arrays (FGPAs) use ________ inputs, resulting in ________ possible outputs.
A.	4,16
B.	8,16
C.	4,12
D.	6,12
Answer» B. 8,16

Discussion

73.	The Altera MAX 7000 series ________.
A.	uses an E2PROM process technology
B.	can have between 2 and 16 LABS and I/O control blocks
C.	is available with DC supply voltages between 2.5 V and 5 V
D.	all of the above
Answer» E.

Discussion

74.	The programming technologies that are used in CPLD devices are all nonvolatile.
A.	1
B.
Answer» B.

Discussion

75.	GAL is an acronym for ________.
A.	Generic Array Logic
B.	General Array Logic
C.	Giant Array Logic
D.	Generic Analysis Logic
Answer» B. General Array Logic

Discussion

76.	How many combinations are handled in an LUT?
A.	4
B.	8
C.	16
D.	32
Answer» D. 32

Discussion

77.	What gives a GAL its flexibility?
A.	Its speed
B.	Its reprogrammable EPROM
C.	Its large logic arrays
D.	Its programmable OLMCs
Answer» E.

Discussion

78.	The ________ can generate any possible logic function of the input variables because it generates every possible AND product term.
A.	GAL
B.	SOP
C.	PROM
D.	LAB
Answer» D. LAB

Discussion

79.	MPGA stands for:
A.	mass produced gated array.
B.	Morgan-Phillips gated array.
C.	memory programmed ROM.
D.	mask programmed ROM.
Answer» E.

Discussion

80.	The macrocells in a PAL/GAL are located ________.
A.	after the programmable AND arrays
B.	ahead of the programmable AND arrays
C.	at the input terminals
D.	at the output terminals
Answer» B. ahead of the programmable AND arrays

Discussion

81.	The Altera UPIX educational development board contains an EP10K60 device in a 280-pin package.
A.	1
B.
Answer» C.

Discussion

82.	Based on the high-density architecture of logic cells, FLEX10K devices are generally classified as HCPLDs.
A.	1
B.
C.	1
D.
Answer» C. 1

Discussion

83.	What does a dot mean when placed on a PLD circuit diagram?
A.	A point that is programmable
B.	A point that cannot change
C.	An intersection of logic blocks
D.	An input or output point
Answer» C. An intersection of logic blocks

Discussion

84.	SPLDs, CPLDs, and FPGAs are all which type of device?
A.	PAL
B.	PLD
C.	EPROM
D.	SRAM
Answer» C. EPROM

Discussion

85.	A PAL16L8 has:
A.	10 inputs and 8 outputs.
B.	8 inputs and 8 outputs.
C.	16 inputs and 16 outputs.
D.	16 inputs and 8 outputs.
Answer» B. 8 inputs and 8 outputs.

Discussion

86.	Which one of the following is an embedded function of the Stratix II FPGA?
A.	AND-OR logic
B.	Programmable SOP
C.	Digital signal processing
D.	None of the above
Answer» D. None of the above

Discussion

87.	The FPLA has a programmable AND array and a programmable OR array.
A.	1
B.
C.	1
D.
Answer» B.

Discussion

88.	Which is a major digital system category?
A.	Standard logic devices
B.	ASICs
C.	Microprocessor/DSP devices
D.	All of the above
Answer» E.

Discussion

89.	Which type of PLD could be used to program basic logic functions?
A.	PLA
B.	PAL
C.	CPLD
D.	all the above
Answer» E.

Discussion

90.	The final step in the device programming sequence is ________.
A.	compiling
B.	downloading
C.	simulation
D.	synthesis
Answer» C. simulation

Discussion

91.	The MAX+PLUS II compiler will automatically program a macrocell to borrow up to six product terms from each of three adjacent macrocells in the same LAB.
A.	1
B.
C.	1
D.
Answer» C. 1

Discussion

92.	An Altera FLEX10K device uses a(n) ________ architecture.
A.	OR array
B.	AND array
C.	OR and AND array
D.	look-up table
Answer» E.

Discussion

93.	A circuit that implements a combinational logic function by storing a list of output values that correspond to all possible input combinations is a(n) ________.
A.	output logic macrocell
B.	look-up table
C.	parallel logic expander
D.	logic element
Answer» C. parallel logic expander

Discussion

94.	PIA is an acronym for ________.
A.	Programmable Interface Array
B.	Post Integrated Array
C.	Programmable Input Array
D.	Programmable Interconnect Array
Answer» E.

Discussion

95.	The complex programmable logic device (CPLD) features a(n) ________ type of memory.
A.	volatile
B.	nonvolatile
C.	EPROM
D.	volitile EPROM
Answer» C. EPROM

Discussion

96.	Now many times can a GAL be erased and reprogrammed?
A.	0
B.	At least 100
C.	At least 1000
D.	Over 10,000
Answer» C. At least 1000

Discussion

97.	Full custom ICs can operate at ________ and require the ________.
A.	lowest speed, largest die area
B.	lowest speed, smallest die area
C.	highest speed, largest die area
D.	highest speed, smallest die area
Answer» E.

Discussion

98.	ASIC stands for:
A.	advanced speed integrated circuit.
B.	advanced standard integrated circuit.
C.	application specific integrated circuit.
D.	application speedy integrated circuit.
Answer» D. application speedy integrated circuit.

Discussion

99.	FPGA is the acronym for ________.
A.	Flexible Programming [of] Generic Assemblies
B.	Field Programmable Generic Array
C.	Field Programmable Gate Array
D.	Field Programmer's Gate Assembly
Answer» D. Field Programmer's Gate Assembly

Discussion

100.	________ are used at the inputs of PAL/GAL devices in order to prevent input loading from a large number of AND gates.
A.	Simplified AND gates
B.	Fuses
C.	Buffers
D.	Latches
Answer» D. Latches

Discussion

Explore topic-wise MCQs in Digital Electronics.

Xilinx software uses triangular symbols called buffers to define pins as input or output.

In a MAX7000S device, when an I/O pin is configured as an input, the associated macrocell can be used for ________.

The GAL16V8 has 32 input variables.

A complex programmable logic device that consists of multiple SPLD arrays with programmable interconnections is called a ________.

The major structures of the MAX7000S are the logic array block (LAB) and the programmable intermediate array (PIA).

In the GAL16V8, the ________ selects the signal that is fed back into the input matrix.

An expensive form of programmable logic is SPLD.

Most PAL devices have a tristate buffer driving the input pins.

The programming technologies that are used in FPGA devices include SRAM, flash, and antifuse, with ________ being the most common.

With microcomputer/DSP systems, devices can be electronically controlled and data can be manipulated by executing a program of instructions that has been written for the application.

Most complex digital designs include ________.

A method for the automated testing of printed circuit boards is called a(n) ________.

The PAL structure is able to perform any sum-of-products (SOP) operation.

The Boolean expression AB + CD is an example of ________.

The PAL has an AND and OR structure similar to a PROM, but in the PAL the inputs to the AND gates are programmable, whereas the inputs to the OR gate are hard-wired.

What is the major downfall of microprocessor/DSP systems?

An SPLD listed as 22V10 has ________.

What is another name for digital circuitry called sequential logic?

A GAL22V10 ________.

Which of the following testing procedures has one or more external moving parts?

PLDs did not gain widespread acceptance with digital until the mid-1980s, when a device called a PAL was introduced.

Most look-up tables in field-programmable gate arrays (FGPAs) use ________ inputs, resulting in ________ possible outputs.

The Altera MAX 7000 series ________.

The programming technologies that are used in CPLD devices are all nonvolatile.

GAL is an acronym for ________.

How many combinations are handled in an LUT?

What gives a GAL its flexibility?

The ________ can generate any possible logic function of the input variables because it generates every possible AND product term.

MPGA stands for:

The macrocells in a PAL/GAL are located ________.

The Altera UPIX educational development board contains an EP10K60 device in a 280-pin package.

Based on the high-density architecture of logic cells, FLEX10K devices are generally classified as HCPLDs.

What does a dot mean when placed on a PLD circuit diagram?

SPLDs, CPLDs, and FPGAs are all which type of device?

A PAL16L8 has:

Which one of the following is an embedded function of the Stratix II FPGA?

The FPLA has a programmable AND array and a programmable OR array.

Which is a major digital system category?

Which type of PLD could be used to program basic logic functions?

The final step in the device programming sequence is ________.

The MAX+PLUS II compiler will automatically program a macrocell to borrow up to six product terms from each of three adjacent macrocells in the same LAB.

An Altera FLEX10K device uses a(n) ________ architecture.

A circuit that implements a combinational logic function by storing a list of output values that correspond to all possible input combinations is a(n) ________.

PIA is an acronym for ________.

The complex programmable logic device (CPLD) features a(n) ________ type of memory.

Now many times can a GAL be erased and reprogrammed?

Full custom ICs can operate at ________ and require the ________.

ASIC stands for:

FPGA is the acronym for ________.

________ are used at the inputs of PAL/GAL devices in order to prevent input loading from a large number of AND gates.

Most look-up tables in field-programmable gate arrays (FGPAs) use inputs, resulting in possible outputs.

Full custom ICs can operate at and require the .