161 + Mcqs in Flip Flops Page 2 McqOptions

51.	The gated S-R flip-flop is asynchronous.
A.	1
B.
Answer» C.

Discussion

52.	When the output of the NOR gate S-R flip-flop is and , the inputs are .
A.	1
B.
Answer» C.

Discussion

53.	A gated S-R flip-flop goes into the CLEAR condition when ________.
A.	S is HIGH; R is LOW; EN is HIGH
B.	S is LOW; R is HIGH; EN is HIGH
C.	S is LOW; R is HIGH; EN is LOW
D.	S is HIGH; R is LOW; EN is LOW
Answer» C. S is LOW; R is HIGH; EN is LOW

Discussion

54.	Edge-triggered J-K flip-flops make it hard for design engineers to know when to accept input data.
A.	1
B.
Answer» C.

Discussion

55.	An input which can only be accepted when an enable or trigger is present is called asynchronous.
A.	1
B.
Answer» C.

Discussion

56.	The J-K flip-flop eliminates the invalid state by toggling when both inputs are high and the clock transitions.
A.	1
B.
Answer» B.

Discussion

57.	It takes four flip-flops to act as a divide-by-4 frequency divider.
A.	1
B.
Answer» C.

Discussion

58.	Inputs that cause the output of a flip-flop to change instantaneously are asynchronous.
A.	1
B.
Answer» B.

Discussion

59.	A one-shot is a special type of multivibrator that must be triggered to produce each output pulse.
A.	1
B.
Answer» B.

Discussion

60.	The Q output of a flip-flop is normally HIGH when the device is in the "CLEAR" or "RESET" state.
A.	1
B.
Answer» C.

Discussion

61.	A gated D latch does not have ________.
A.	a clock input
B.	an enable input
C.	a output
D.	steering gates
Answer» B. an enable input

Discussion

62.	A positive edge-triggered flip-flop will accept inputs only when the clock ________.
A.	is LOW
B.	changes from HIGH to LOW
C.	is HIGH
D.	changes from LOW to HIGH
Answer» E.

Discussion

63.	The circuit given below fails to function; the inputs are checked with a logic probe and the following indications are obtained: CLK, J1, J2, J3, K1, K2, and K3 are pulsing. Q and are HIGH. and PRE are LOW. What could be causing the problem?
A.	There is no problem.
B.	The clock should be held HIGH.
C.	The PRE is stuck LOW.
D.	The CLR is stuck HIGH.
Answer» D. The CLR is stuck HIGH.

Discussion

64.	The timing network that sets the output frequency of a 555 astable circuit contains ________.
A.	three external resistors are used
B.	two external resistors and an external capacitor are used
C.	an external resistor and two external capacitors are used
D.	no external resistor or capacitor is required
Answer» C. an external resistor and two external capacitors are used

Discussion

65.	An invalid condition in the operation of an active-HIGH input S-R latch occurs when ________.
A.	HIGHs are applied simultaneously to both inputs S and R
B.	LOWs are applied simultaneously to both inputs S and R
C.	a LOW is applied to the S input while a HIGH is applied to the R input
D.	a HIGH is applied to the S input while a LOW is applied to the R input
Answer» B. LOWs are applied simultaneously to both inputs S and R

Discussion

66.	A flip-flop's normal starting state when power is first applied to a circuit is always the SET state.
A.	1
B.
C.	1
D.
Answer» C. 1

Discussion

67.	What is the significance of the J and K terminals on the J-K flip-flop?
A.	There is no known significance in their designations.
B.	The J represents "jump," which is how the Q output reacts whenever the clock goes high and the J input is also HIGH.
C.	The letters were chosen in honor of Jack Kilby, the inventory of the integrated circuit.
D.	All of the other letters of the alphabet are already in use.
Answer» D. All of the other letters of the alphabet are already in use.

Discussion

68.	The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________.
A.	parity error checking
B.	ones catching
C.	digital discrimination
D.	digital filtering
Answer» C. digital discrimination

Discussion

69.	Most people would prefer to use ________ over HDL.
A.	graphic descriptions
B.	functions
C.	VHDL
D.	AHDL
Answer» B. functions

Discussion

70.	Pulse-triggered flip-flops are identified by a bubble on the Q output terminal.
A.	1
B.
C.	1
D.
Answer» C. 1

Discussion

71.	If an input is activated by a signal transition, it is ________.
A.	edge-triggered
B.	toggle triggered
C.	clock triggered
D.	noise triggered
Answer» B. toggle triggered

Discussion

72.	An RC circuit used in a nonretriggerable 74121 one-shot has an REXT of 49 k and a CEXT of 0.2 F. The pulse width (tW) is approximately ________.
A.	6.9 s
B.	6.9 ms
C.	69 ms
D.	690 ms
Answer» C. 69 ms

Discussion

73.	If data is brought into the J terminal and its complement to the K terminal, a J-K flip-flop operates as a(n) ________.
A.	S-C flip-flop
B.	D flip-flop
C.	gated S-C flip-flop
D.	TOGGLE flip-flop
Answer» C. gated S-C flip-flop

Discussion

74.	For an S-R flip-flop to be set or reset, the respective input must be:
A.	installed with steering diodes
B.	in parallel with a limiting resistor
C.	LOW
D.	HIGH
Answer» E.

Discussion

75.	Which of the following best describes the action of pulse-triggered FF's?
A.	The clock and the S-R inputs must be pulse shaped.
B.	The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.
C.	A pulse on the clock transfers data from input to output.
D.	The synchronous inputs must be pulsed.
Answer» C. A pulse on the clock transfers data from input to output.

Discussion

76.	A 555 operating as a monostable multivibrator has an R1 of 220 k. Determine C1 for a pulse width of 4 ms.
A.	0.017 F
B.	17 pF
C.	170 pF
D.	1,700 F
Answer» B. 17 pF

Discussion

77.	A J-K flip-flop is in a "no change" condition when ________.
A.	J = 1, K = 1
B.	J = 1, K = 0
C.	J = 0, K = 1
D.	J = 0, K = 0
Answer» E.

Discussion

78.	How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?
A.	It can't be done.
B.	Invert the Q outputs.
C.	Invert the S-R inputs.
Answer» D.

Discussion

79.	A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?
A.	The power supply is probably noisy.
B.	The switch contacts are bouncing.
C.	The socket contacts on the register IC are corroded.
D.	The register IC is intermittent and failure is imminent.
Answer» C. The socket contacts on the register IC are corroded.

Discussion

80.	A 555 operating as a monostable multivibrator has an R1 of 1 M. Determine C1 for a pulse width of 2 s.
A.	1.8 F
B.	18 F
C.	18 pF
D.	18 nF
Answer» B. 18 F

Discussion

81.	Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________.
A.	0
B.	11
C.	1
D.	10
Answer» B. 11

Discussion

82.	All multivibrators require feedback.
A.	1
B.
C.	1
D.
Answer» B.

Discussion

83.	Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.
A.	1
B.
Answer» C.

Discussion

84.	The output of a gated S-R flip-flop changes only if the:
A.	flip-flop is set
B.	control input data has changed
C.	flip-flop is reset
D.	input data has no change
Answer» C. flip-flop is reset

Discussion

85.	The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as a ________.
A.	FUNCTION
B.	logic primitive
C.	VARIABLE
D.	PROCESS
Answer» C. VARIABLE

Discussion

86.	A TOGGLE input to a J-K flip-flop causes the Q and outputs to switch to their opposite state.
A.	1
B.
C.	1
D.
Answer» B.

Discussion

87.	On a master-slave flip-flop, when is the master enabled?
A.	when the gate is LOW
B.	when the gate is HIGH
C.	both of the above
D.	neither of the above
Answer» C. both of the above

Discussion

88.	When is a flip-flop said to be transparent?
A.	when the Q output is opposite the input
B.	when the Q output follows the input
C.	when you can see through the IC packaging
Answer» C. when you can see through the IC packaging

Discussion

89.	An astable multivibrator is a circuit that ________.
A.	has two stable states
B.	is free-running
C.	produces a continuous output signal
D.	is free-running and produces a continuous output signal
Answer» D. is free-running and produces a continuous output signal

Discussion

90.	In VHDL, how many inputs will a primitive JK flip-flop have?
A.	2
B.	3
C.	4
D.	5
Answer» E.

Discussion

91.	A negative edge-triggered flip-flop will accept inputs only when the clock is LOW.
A.	1
B.
Answer» C.

Discussion

92.	A 555 operating as a monostable multivibrator has a C1 = 0.01 F. Determine R1 for a pulse width of 2 ms.
A.	200 k
B.	182 k
C.	91 k
D.	182
Answer» C. 91 k

Discussion

93.	What is the difference between the enable input of the 7475 and the clock input of the 7474?
A.	The 7475 is edge-triggered.
B.	The 7474 is edge-triggered.
Answer» C.

Discussion

94.	A positive edge-triggered D flip-flop will store a 1 when ________.
A.	the D input is HIGH and the clock transitions from HIGH to LOW
B.	the D input is HIGH and the clock transitions from LOW to HIGH
C.	the D input is HIGH and the clock is LOW
D.	the D input is HIGH and the clock is HIGH
Answer» C. the D input is HIGH and the clock is LOW

Discussion

95.	Pulse-triggered or level-triggered devices are the same.
A.	1
B.
C.	1
D.
Answer» B.

Discussion

96.	Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?
A.	active-HIGH
B.	active-LOW
Answer» B. active-LOW

Discussion

97.	A gated S-R latch and its associated waveforms are shown below. What, if anything, is wrong and what could be causing the problem?
A.	The output is always low; the circuit is defective.
B.	The Q output should be the complement of the output; the S and R terminals are reversed.
C.	The Q should be following the R input; the R input is defective.
D.	There is nothing wrong with the circuit.
Answer» B. The Q output should be the complement of the output; the S and R terminals are reversed.

Discussion

98.	As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:
A.	very long.
B.	very short.
C.	at a maximum value to enable the input control signals to stabilize.
D.	of no consequence as long as the levels are within the determinate range of value.
Answer» C. at a maximum value to enable the input control signals to stabilize.

Discussion

99.	A 555 operating as a monostable multivibrator has a C1 = 100 F. Determine R1 for a pulse width of 500 ms.
A.	45
B.	455
C.	4.5 k
D.	455 k
Answer» D. 455 k

Discussion

100.	Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________.
A.	1 kHz
B.	2 kHz
C.	4 kHz
D.	16 kHz
Answer» C. 4 kHz

Discussion

Explore topic-wise MCQs in Digital Electronics.

The gated S-R flip-flop is asynchronous.

When the output of the NOR gate S-R flip-flop is and , the inputs are .

A gated S-R flip-flop goes into the CLEAR condition when ________.

Edge-triggered J-K flip-flops make it hard for design engineers to know when to accept input data.

An input which can only be accepted when an enable or trigger is present is called asynchronous.

The J-K flip-flop eliminates the invalid state by toggling when both inputs are high and the clock transitions.

It takes four flip-flops to act as a divide-by-4 frequency divider.

Inputs that cause the output of a flip-flop to change instantaneously are asynchronous.

A one-shot is a special type of multivibrator that must be triggered to produce each output pulse.

The Q output of a flip-flop is normally HIGH when the device is in the "CLEAR" or "RESET" state.

A gated D latch does not have ________.

A positive edge-triggered flip-flop will accept inputs only when the clock ________.

The circuit given below fails to function; the inputs are checked with a logic probe and the following indications are obtained: CLK, J1, J2, J3, K1, K2, and K3 are pulsing. Q and are HIGH. and PRE are LOW. What could be causing the problem?

The timing network that sets the output frequency of a 555 astable circuit contains ________.

An invalid condition in the operation of an active-HIGH input S-R latch occurs when ________.

A flip-flop's normal starting state when power is first applied to a circuit is always the SET state.

What is the significance of the J and K terminals on the J-K flip-flop?

The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________.

Most people would prefer to use ________ over HDL.

Pulse-triggered flip-flops are identified by a bubble on the Q output terminal.

If an input is activated by a signal transition, it is ________.

An RC circuit used in a nonretriggerable 74121 one-shot has an REXT of 49 k and a CEXT of 0.2 F. The pulse width (tW) is approximately ________.

If data is brought into the J terminal and its complement to the K terminal, a J-K flip-flop operates as a(n) ________.

For an S-R flip-flop to be set or reset, the respective input must be:

Which of the following best describes the action of pulse-triggered FF's?

A 555 operating as a monostable multivibrator has an R1 of 220 k. Determine C1 for a pulse width of 4 ms.

A J-K flip-flop is in a "no change" condition when ________.

How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?

A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?

A 555 operating as a monostable multivibrator has an R1 of 1 M. Determine C1 for a pulse width of 2 s.

Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________.

All multivibrators require feedback.

Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.

The output of a gated S-R flip-flop changes only if the:

The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as a ________.

A TOGGLE input to a J-K flip-flop causes the Q and outputs to switch to their opposite state.

On a master-slave flip-flop, when is the master enabled?

When is a flip-flop said to be transparent?

An astable multivibrator is a circuit that ________.

In VHDL, how many inputs will a primitive JK flip-flop have?

A negative edge-triggered flip-flop will accept inputs only when the clock is LOW.

A 555 operating as a monostable multivibrator has a C1 = 0.01 F. Determine R1 for a pulse width of 2 ms.

What is the difference between the enable input of the 7475 and the clock input of the 7474?

A positive edge-triggered D flip-flop will store a 1 when ________.

Pulse-triggered or level-triggered devices are the same.

Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?

A gated S-R latch and its associated waveforms are shown below. What, if anything, is wrong and what could be causing the problem?

As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:

A 555 operating as a monostable multivibrator has a C1 = 100 F. Determine R1 for a pulse width of 500 ms.

Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________.