The gated S-R flip-flop is asynchronous. – McqOptions

MCQOPTIONS

1.	The gated S-R flip-flop is asynchronous.
A.	1
B.
Answer» C.

Discussion

No Comment Found

Related MCQs

An active-HIGH input S-R latch has a 1 on the S input and a 0 on the R input. What state is the latch in?
Assume an latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ________.
A flip-flop operation is described as a toggle when the result after a clock is ________.
The term hold always means ________.
A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ mS.
ICs can perform sequential operations, including counting and data shifting.
The major advantage of a Schmitt trigger input is that it ________.
The point(s) on this timing diagram where the Q output of a D latch will be HIGH is/are ________.
The advantage of a J-K flip-flop over an S-R FF is that ________.
The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as logic standard primitives.