MCQOPTIONS
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MCQOPTIONS
This section includes 249 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Electronics knowledge and support exam preparation. Choose a topic below to get started.
| 101. |
In an all NOR gate realization of a combinational circuit all EVEN and ODD level gates behave like |
| A. | OR and AND |
| B. | AND and OR |
| C. | OR and NOT |
| D. | NOR and AND |
| Answer» C. OR and NOT | |
| 102. |
If only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables, what is the maximum size of the multiplexer needed? |
| A. | 2n-2 line to 1 line |
| B. | 2n-1 line to 1 line |
| C. | 2n + 1 line to 1 line |
| D. | 2n + 2 line to 1 line |
| Answer» C. 2n + 1 line to 1 line | |
| 103. |
How many 3 – to – 8 line decoders with enable output are needed to construct a 6 – to – 64 line decoder without using any other logic gates? |
| A. | 7 |
| B. | 8 |
| C. | 9 |
| D. | 10 |
| Answer» D. 10 | |
| 104. |
A 16-bit serial adder needs how many Full Adders? |
| A. | 3 |
| B. | 1 |
| C. | 2 |
| D. | 0 |
| Answer» C. 2 | |
| 105. |
For a binary half-subtractor having two inputs A and B, the correct set of logical expression for the outputs D (= A minus B) and X (= borrow) are |
| A. | \(D=AB+A\bar B,X=\bar AB\) |
| B. | \(D=A\bar B+A\bar B ,X=A\bar B\) |
| C. | \(D=A \bar B+\bar AB ,X=\bar AB\) |
| D. | \(D=AB+A \bar B,X=A\bar B\) |
| Answer» D. \(D=AB+A \bar B,X=A\bar B\) | |
| 106. |
In the circuit shown, |
| A. | F = WX̅ + W̅X + Y̅Z̅ |
| B. | F = WX̅ + W̅X + Y̅Z |
| C. | F = WX̅Y̅ + W̅XY̅ |
| D. | F = (W̅ + X̅) X̅Z̅ |
| Answer» D. F = (W̅ + X̅) X̅Z̅ | |
| 107. |
No. of flip-flops used in decade counter |
| A. | 3 |
| B. | 2 |
| C. | 4 |
| D. | None of these |
| Answer» D. None of these | |
| 108. |
Identify the combinational logic circuit(s) from the following list:I. Full adderII. J-K flip-flopIII. Counter |
| A. | II only |
| B. | III only |
| C. | II and III |
| D. | I only |
| Answer» E. | |
| 109. |
Consider 4-bit gray code representation of numbers. Let h3 h2 h1 h0 be the gray code representation of a number n and g1g2g3g0 be the gray code representation of the number (n + 1) modulo 16. Which one of the following functions is correct? |
| A. | g0 (h3 h2 h1 h0) = Σ(1,2,3,6,10,13,14,15) |
| B. | g1 (h3 h2 h1 h0) = Σ(4,9,10,11,12,13,14,15) |
| C. | g2 (h3 h2 h1 h0) = Σ(2,4,5,6,7,12,13,15) |
| D. | g3 (h3 h2 h1 h0) = Σ(0,1,6,7,10,11,12,13) |
| Answer» D. g3 (h3 h2 h1 h0) = Σ(0,1,6,7,10,11,12,13) | |
| 110. |
Consider the multiplexer based logic circuit shown in the figure.Which one of the following Boolean functions is realized by the circuit? |
| A. | F = W S̅1S̅2 |
| B. | F = WS1 + WS2 + S1S2 |
| C. | F = W̅ + S1 + S2 |
| D. | F = W ⊕ S1 ⊕ S2 |
| Answer» E. | |
| 111. |
How many inputs & outputs does a full adder have? |
| A. | 3, 2 |
| B. | 2, 3 |
| C. | 3, 3 |
| D. | 2, 2 |
| Answer» B. 2, 3 | |
| 112. |
In a decoder, if the input lines are 4 then number of maximum output lines will be: |
| A. | 2 |
| B. | 16 |
| C. | 4 |
| D. | 8 |
| Answer» C. 4 | |
| 113. |
For an n-bit binary adder, what is the number of gates through which a carry has to propagate from input to output? |
| A. | n |
| B. | 2n |
| C. | n2 |
| D. | n + 1 |
| Answer» C. n2 | |
| 114. |
Half adder is also known as |
| A. | NAND |
| B. | AND |
| C. | NOT |
| D. | XOR |
| Answer» E. | |
| 115. |
A 3-bit gray counter is used to control the output of the multiplexer as shown in the figure. The initial state of the counter is 0002. The output is pulled high. The output of the circuit follows the sequence |
| A. | I0, 1, 1, I1, I3, 1, 1, I2 |
| B. | I0, 1, I1, 1, I2, 1, I3, 1 |
| C. | 1, I0, 1, I1, I2, 1, I3, 1 |
| D. | I0, I1, I2, I3, I0, I1, I2, I3 |
| Answer» B. I0, 1, I1, 1, I2, 1, I3, 1 | |
| 116. |
Following Multiplexer circuit is equivalent to |
| A. | Sum equation of full adder |
| B. | Carry equation of full adder |
| C. | Borrow equation for full subtractor |
| D. | None of these |
| Answer» B. Carry equation of full adder | |
| 117. |
Identify the given circuit diagram. |
| A. | Full adder |
| B. | Half adder |
| C. | Carry look ahead adder |
| D. | Ripple carry adder |
| Answer» D. Ripple carry adder | |
| 118. |
Number of control lines required for 16 to 1 multiplexer is |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 16 |
| Answer» D. 16 | |
| 119. |
Consider the circuit shown in the figure.The Boolean expression F implemented by the circuit is |
| A. | \(\bar X\bar Y\bar Z + XY + \bar YZ\) |
| B. | \(\bar XY\bar Z + XZ + \bar YZ\) |
| C. | \(\bar XY\bar Z + XY + \bar YZ\) |
| D. | \(\bar X\bar Y\bar Z + XZ + \bar YZ\) |
| Answer» C. \(\bar XY\bar Z + XY + \bar YZ\) | |
| 120. |
In a half – adder having two inputs A and B and two outputs (S and C are the sum and carry output bits respectively) the Boolean expression for S and C in terms of A and B is |
| A. | \(S = \bar AB + A\bar B;C = AB\) |
| B. | \(S = AB + \bar AB;C = A + B\) |
| C. | \(S = \bar A\bar B + AB;C = A + \bar B\) |
| D. | \(S = \bar A + A\bar B;C = \bar A + B\) |
| Answer» B. \(S = AB + \bar AB;C = A + B\) | |
| 121. |
Consider the following combinational function block involving four Boolean variables x, y, a, b where x, a, b are inputs and y is the output.f (x, y, a, b)( if (x is 1) y = a; else y = b;}Which one of the following digital logic blocks is the most suitable for implementing this function? |
| A. | Full adder |
| B. | Priority encoder |
| C. | Multiplexer |
| D. | Flip-flop |
| Answer» D. Flip-flop | |
| 122. |
In the digital circuit given below, F is |
| A. | XY + YZ̅ |
| B. | XY + Y̅Z |
| C. | X̅Y̅ + YZ̅ |
| D. | XZ + Y̅ |
| Answer» C. X̅Y̅ + YZ̅ | |
| 123. |
A bus organized processor consists of 15 registers. The number of selection lines in each multiplexer and in the destination decoder are respectively: |
| A. | 2 and 4 |
| B. | 4 and 2 |
| C. | 4 and 4 |
| D. | 4 and 8 |
| Answer» D. 4 and 8 | |
| 124. |
Direction: Given question consists of two statements, one labeled as the 'Assertion (A)' and the other as 'Reason (R)'. You are to examine these two statements carefully and select the answers to these items using the codes given below.Assertion (A): A look-ahead carry adder is a fast adder.Reason (R): A parallel carry adder generates the sum digits directly from the input digits. |
| A. | Both A and R are individually true and R is the correct explanation of A |
| B. | Both A and R are individually true but R is NOT the correct explanation of A |
| C. | A is true but R is false |
| D. | A is false but R is true |
| Answer» B. Both A and R are individually true but R is NOT the correct explanation of A | |
| 125. |
How many input lines are there in a ‘Full Adder’? |
| A. | 2 |
| B. | 4 |
| C. | 1 |
| D. | 3 |
| Answer» E. | |
| 126. |
In a half adder, the carry output is high if the inputs are: |
| A. | 1, 1 |
| B. | 0, 0 |
| C. | 0, 1 |
| D. | 1, 0 |
| Answer» B. 0, 0 | |
| 127. |
How many bits can be compared in parallel using one 74LS85 chip? |
| A. | 3 |
| B. | 2 |
| C. | 4 |
| D. | 8 |
| Answer» D. 8 | |
| 128. |
An \(\rm 8-to-1\) multiplexer is used to implement a logical function \(\rm Y\) as shown in the figure. Then the output \(\rm Y\) is given by |
| A. | \(\rm Y = A\bar BC + A\bar CD\) |
| B. | \(\rm Y = \bar ABC + A\bar BD\) |
| C. | \(\rm Y = AB\bar C + \bar ACD\) |
| D. | \(\rm Y = \bar A\bar BD + A\bar BC\) |
| Answer» D. \(\rm Y = \bar A\bar BD + A\bar BC\) | |
| 129. |
A half adder has |
| A. | 2 inputs and 2 outputs |
| B. | 2 inputs and 3 outputs |
| C. | 3 inputs and 3 outputs |
| D. | 1 input and 1 output |
| Answer» B. 2 inputs and 3 outputs | |
| 130. |
A 4-bit XS-3 parallel adder needs_____ 4-bit parallel adder IC 74LS83s. |
| A. | 3 |
| B. | 2 |
| C. | 4 |
| D. | 1 |
| Answer» C. 4 | |
| 131. |
A combinational logic circuit that is used when it is desired to send data from two or more source through a single transmission line is known as _________. |
| A. | Encoder |
| B. | Multiplexer |
| C. | Decoder |
| D. | Demultiplexer |
| Answer» C. Decoder | |
| 132. |
An array multiplier is used to find the product of a 3-bit number with a 4-bit number. How many 4 bits addresses are required to perform multiplication? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» C. 3 | |
| 133. |
For the box shown the output D is true if and only if a majority of the inputs are true.The Boolean function for the output is: |
| A. | D = ABC̅ + A̅BC + AB̅C |
| B. | D = ABC + A̅BC + AB̅C + ABC̅ |
| C. | D = A̅B̅C̅ +AB + AC + BC |
| D. | D = A̅B̅C + AB̅C̅ + A̅BC̅ + ABC |
| Answer» C. D = A̅B̅C̅ +AB + AC + BC | |
| 134. |
Encoder |
| A. | Assigns quantized values |
| B. | Changes quantized values to binary values |
| C. | Changes quantized values to numerical values |
| D. | Changes numerical values to binary values |
| Answer» C. Changes quantized values to numerical values | |
| 135. |
Based on the paragraph given below answer the following question:The traditional methods of combinational circuits involve simplification and realization using gates. Using these methods, complex functions have been integrated and are easily available in IC form. There is an attractive array of devices like a multiplexer, demultiplexer, decoders, comparators, parity generators/checkers, which significantly reduce IC package count there by reducing the system cost. The system design is greatly simplified because the laborious and time-consuming simplification methods are generally not required with these devices. This also improves the reliability of the system by reducing the number of external wired connections. But they have some limitations as well. Different memories like ROM, PROM can also be used to implement combinational circuits without much simplification. Consider the following digital circuits.1. Multiplexers2. Read Only Memories3. D-latch4. Circuit as shown in figure belowWhich of these come under the class of combinational circuits? |
| A. | 1 and 2 |
| B. | 3 and 4 |
| C. | 1, 2 and 3 |
| D. | 1, 2 3 and 4 |
| Answer» B. 3 and 4 | |
| 136. |
The 7447A is a BCD-to-7-segment decoder with ripple blanking input and output functions. The purpose of these lines is to ________. |
| A. | turn off the display for any nonsignificant digit |
| B. | turn off the display for any zero |
| C. | turn off the display for leading or trailing zeros |
| D. | test the display to assure all segments are operational |
| Answer» B. turn off the display for any zero | |
| 137. |
In an odd-parity system, the data that will produce a parity bit = 1 is ________. |
| A. | data = 1010011 |
| B. | data = 1111000 |
| C. | data = 1100000 |
| D. | All of the above |
| Answer» E. | |
| 138. |
The abbreviation for an exclusive-OR gate is XOR. |
| A. | 1 |
| B. | |
| Answer» B. | |
| 139. |
To subtract a signed number (the subtrahend) from another signed number (the minuend) in the 2's complement system, the minuend is ________. |
| A. | complemented only if it is positive |
| B. | complemented only if it is negative |
| C. | always complemented |
| D. | never complemented |
| Answer» E. | |
| 140. |
A square in the top row of a K-map is considered to be adjacent to its corresponding square in the bottom row. |
| A. | 1 |
| B. | |
| Answer» B. | |
| 141. |
The following combination is correct for an ODD parity data transmission system: data = 011011100 and parity = 0 |
| A. | 1 |
| B. | |
| Answer» B. | |
| 142. |
A 4-bit adder has the following inputs: C0 = 0, A1 = 0, A2 = 1, A3 = 0, A4 = 1, B1 = 0, B2 = 1, B3 = 1, B4 = 1. The output will be ________. |
| A. | 1100 |
| B. | 10101 |
| C. | 11000 |
| D. | 11 |
| Answer» D. 11 | |
| 143. |
To implement the full-adder sum functions, two exclusive-OR gates can be used. |
| A. | 1 |
| B. | |
| Answer» B. | |
| 144. |
The K-map provides a "graphical" approach to simplifying sum-of-products expressions. |
| A. | 1 |
| B. | |
| Answer» B. | |
| 145. |
Occasionally, a particular logic expression will be of no consequence in the operation of a circuit, such as in a BCD-to-decimal converter. These result in ________ terms in the K-map and can be treated as either ________ or ________, in order to ________ the resulting term. |
| A. | don't care, 1's, 0's, simplify |
| B. | spurious, AND's, OR's, eliminate |
| C. | duplicate, 1's, 0's, verify |
| D. | spurious, 1's, 0's, simplify |
| Answer» B. spurious, AND's, OR's, eliminate | |
| 146. |
When decisions demand two possible actions, the IF/THEN/ELSE control structure is used. |
| A. | 1 |
| B. | |
| Answer» B. | |
| 147. |
Two 4-bit comparators are cascaded to form an 8-bit comparator. The cascading inputs of the most significant 4 bits should be connected ________. |
| A. | to the outputs from the least significant 4-bit comparator |
| B. | to the cascading inputs of the least significant 4-bit comparator |
| C. | A = B to a logic high, A < b and a > B to a logic low |
| D. | ground |
| Answer» B. to the cascading inputs of the least significant 4-bit comparator | |
| 148. |
The K-map in the figure below shows the correct implementation of the expression X = ACD + AB(CD + BC). |
| A. | 1 |
| B. | |
| Answer» C. | |
| 149. |
The addition of two signed numbers in the 2's complement system can cause overflow. For overflow to occur both numbers must ________. |
| A. | be positive |
| B. | be negative |
| C. | have the same sign |
| D. | have opposite signs |
| Answer» D. have opposite signs | |
| 150. |
A pull-up resistor is a resistor used to keep a given point in a circuit HIGH when in the active state. |
| A. | 1 |
| B. | |
| Answer» B. | |