MCQOPTIONS
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MCQOPTIONS
This section includes 99 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Electronics knowledge and support exam preparation. Choose a topic below to get started.
| 51. |
How many clock pulses will be required to completely load serially a 5-bit shift register? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» E. | |
| 52. |
In a 4-bit Johnson counter sequence there are a total of how many states, or bit patterns? |
| A. | 1 |
| B. | 2 |
| C. | 4 |
| D. | 8 |
| Answer» E. | |
| 53. |
The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state 11110000. After two clock pulses, the register contains ________. |
| A. | 10111000 |
| B. | 10110111 |
| C. | 11110000 |
| D. | 11111100 |
| Answer» E. | |
| 54. |
A parallel load operation is asynchronous, so it is not dependent on the clock. |
| A. | 1 |
| B. | |
| Answer» B. | |
| 55. |
A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________. |
| A. | 0 |
| B. | 1111 |
| C. | 111 |
| D. | 1000 |
| Answer» D. 1000 | |
| 56. |
What does the output enable do on the 74395A chip? |
| A. | It determines when data can be loaded. |
| B. | It forces all outputs to go HIGH. |
| C. | It forces all outputs to go LOW. |
| D. | It activates the three-state buffer. |
| Answer» E. | |
| 57. |
What type of register would have a complete binary number shifted in one bit at a time and have all the stored bits shifted out one at a time? |
| A. | parallel-in, parallel-out |
| B. | parallel-in, serial-out |
| C. | serial-in, parallel-out |
| D. | serial-in, serial-out |
| Answer» D. serial-in, serial-out | |
| 58. |
An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________. |
| A. | 16 s |
| B. | 8 s |
| C. | 4 s |
| D. | 2 s |
| Answer» D. 2 s | |
| 59. |
A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________ position(s) for each clock pulse. |
| A. | right, one |
| B. | right, two |
| C. | left, one |
| D. | left, three |
| Answer» B. right, two | |
| 60. |
The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out shift register that is initially clear. What are the Q outputs after four clock pulses? |
| A. | 10011100 |
| B. | 11000000 |
| C. | 1100 |
| D. | 11110000 |
| Answer» C. 1100 | |
| 61. |
A ring counter is a register in which a certain pattern of 1s and 0s is continuously outputted in parallel. |
| A. | 1 |
| B. | |
| C. | 1 |
| D. | |
| Answer» B. | |
| 62. |
To operate correctly, starting a ring shift counter requires: |
| A. | clearing all the flip-flops |
| B. | presetting one flip-flop and clearing all others |
| C. | clearing one flip-flop and presetting all others |
| D. | presetting all the flip-flops |
| Answer» C. clearing one flip-flop and presetting all others | |
| 63. |
What is meant by parallel load of a shift register? |
| A. | All FFs are preset with data. |
| B. | Each FF is loaded with data, one at a time. |
| Answer» B. Each FF is loaded with data, one at a time. | |
| 64. |
To serially shift a nibble (four bits) of data into a shift register, there must be ________. |
| A. | one clock pulse |
| B. | four clock pulses |
| C. | eight clock pulses |
| D. | one clock pulse for each 1 in the data |
| Answer» C. eight clock pulses | |
| 65. |
A 4-bit ring counter is loaded with a single 1. The frequency of any given output is ________. |
| A. | the same as the clock |
| B. | twice the clock frequency |
| C. | one-half the clock frequency |
| D. | one-fourth the clock frequency |
| Answer» E. | |
| 66. |
What is a transceiver circuit? |
| A. | a buffer that transfers data from input to output |
| B. | a buffer that transfers data from output to input |
| C. | a buffer that can operate in both directions |
| Answer» D. | |
| 67. |
A type of shift register that requires access to the Q outputs of all stages is ________. |
| A. | parallel in/serial out |
| B. | serial in/parallel out |
| C. | serial in/serial out |
| D. | a bidirectional shift register |
| Answer» C. serial in/serial out | |
| 68. |
What is the difference between a ring shift counter and a Johnson shift counter? |
| A. | There is no difference. |
| B. | A ring is faster. |
| C. | The feedback is reversed. |
| D. | The Johnson is faster. |
| Answer» D. The Johnson is faster. | |
| 69. |
What is the difference between a shift-right register and a shift-left register? |
| A. | There is no difference. |
| B. | the direction of the shift |
| Answer» C. | |
| 70. |
In a 6-bit Johnson counter sequence there are a total of how many states, or bit patterns? |
| A. | 2 |
| B. | 6 |
| C. | 12 |
| D. | 24 |
| Answer» D. 24 | |
| 71. |
A Johnson counter, constructed with N flip-flops, has how many unique states? |
| A. | N |
| B. | 2N |
| C. | 2N |
| D. | N2 |
| Answer» C. 2N | |
| 72. |
When is it important to use a three-state buffer? |
| A. | when two or more outputs are connected to the same input |
| B. | when all outputs are normally HIGH |
| C. | when all outputs are normally LOW |
| D. | when two or more outputs are connected to two or more inputs |
| Answer» B. when all outputs are normally HIGH | |
| 73. |
To keep output data accurate, 4-bit series-in, parallel-out shift registers employ a ________. |
| A. | divide-by-4 clock pulse |
| B. | sequence generator |
| C. | strobe line |
| D. | multiplexer |
| Answer» D. multiplexer | |
| 74. |
If an 8-bit ring counter has an initial state 10111110, what is the state after the fourth clock pulse? |
| A. | 11101011 |
| B. | 10111 |
| C. | 11110000 |
| D. | 0 |
| Answer» B. 10111 | |
| 75. |
Another way to connect devices to a shared data bus is to use a ________. |
| A. | circulating gate |
| B. | transceiver |
| C. | bidirectional encoder |
| D. | strobed latch |
| Answer» C. bidirectional encoder | |
| 76. |
A stepper motor makes its rotation in smooth continuous motion. |
| A. | 1 |
| B. | |
| C. | 1 |
| D. | |
| Answer» C. 1 | |
| 77. |
Ring shift and Johnson counters are: |
| A. | synchronous counters |
| B. | aynchronous counters |
| C. | true binary counters |
| D. | synchronous and true binary counters |
| Answer» B. aynchronous counters | |
| 78. |
Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) |
| A. | 1100 |
| B. | 11 |
| C. | 0 |
| D. | 1111 |
| Answer» D. 1111 | |
| 79. |
A ferromagnetic material is one that forms a resistance to magnetic fields. |
| A. | 1 |
| B. | |
| Answer» C. | |
| 80. |
A type of shift register in which the Q or Q output of one stage is not connected to the input of the next stage is ________. |
| A. | parallel in/serial out |
| B. | serial in/parallel out |
| C. | serial in/serial out |
| D. | parallel in/parallel out |
| Answer» E. | |
| 81. |
What is the preset condition for a ring shift counter? |
| A. | all FFs set to 1 |
| B. | all FFs cleared to 0 |
| C. | a single 0, the rest 1 |
| D. | a single 1, the rest 0 |
| Answer» E. | |
| 82. |
A counter has a specified sequence of states, but a shift register does not. |
| A. | 1 |
| B. | |
| Answer» B. | |
| 83. |
With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________. |
| A. | 4 μs |
| B. | 40 μs |
| C. | 400 μs |
| D. | 40 ms |
| Answer» C. 400 Œºs | |
| 84. |
When an 8-bit serial in/serial out shift register is used for a 20 s time delay, the clock frequency is ________. |
| A. | 40 kHz |
| B. | 50 kHz |
| C. | 400 kHz |
| D. | 500 kHz |
| Answer» D. 500 kHz | |
| 85. |
With a 50 kHz clock frequency, six bits can be serially entered into a shift register in ________. |
| A. | 12 s |
| B. | 120 s |
| C. | 12 ms |
| D. | 120 ms |
| Answer» C. 12 ms | |
| 86. |
A modulus-12 ring counter requires a minimum of ________. |
| A. | 10 flip-flops |
| B. | 12 flip-flops |
| C. | 6 flip-flops |
| D. | 2 flip-flops |
| Answer» C. 6 flip-flops | |
| 87. |
One of the stages in a register consists of a latch. |
| A. | 1 |
| B. | |
| C. | 1 |
| D. | |
| Answer» B. | |
| 88. |
A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________. |
| A. | 1110 |
| B. | 111 |
| C. | 1000 |
| D. | 1001 |
| Answer» E. | |
| 89. |
What is a shift register that will accept a parallel input, or a bidirectional serial load and internal shift features, called? |
| A. | tristate |
| B. | end around |
| C. | universal |
| D. | conversion |
| Answer» D. conversion | |
| 90. |
How can parallel data be taken out of a shift register simultaneously? |
| A. | Use the Q output of the first FF. |
| B. | Use the Q output of the last FF. |
| C. | Tie all of the Q outputs together. |
| D. | Use the Q output of each FF. |
| Answer» E. | |
| 91. |
On the third clock pulse, a 4-bit Johnson sequence is Q0 = 1, Q1 = 1, Q2 = 1, and Q3 = 0. On the fourth clock pulse, the sequence is ________. |
| A. | Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 1 |
| B. | Q0 = 1, Q1 = 1, Q2 = 0, Q3 = 0 |
| C. | Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0 |
| D. | Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 0 |
| Answer» B. Q0 = 1, Q1 = 1, Q2 = 0, Q3 = 0 | |
| 92. |
What are the three output conditions of a three-state buffer? |
| A. | HIGH, LOW, float |
| B. | 1, 0, float |
| C. | both of the above |
| D. | neither of the above |
| Answer» D. neither of the above | |
| 93. |
A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing ________. |
| A. | 1101 |
| B. | 111 |
| C. | 1 |
| D. | 1110 |
| Answer» C. 1 | |
| 94. |
How would a latch circuit be used in a microprocessor system? |
| A. | as transportation for Intel employees |
| B. | for a group of data that is the same |
| C. | as a set of common connections for transfer of data |
| D. | right, one |
| Answer» D. right, one | |
| 95. |
The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses? |
| A. | 0 |
| B. | 10 |
| C. | 1000 |
| D. | 1111 |
| Answer» D. 1111 | |
| 96. |
Which type of device may be used to interface a parallel data format with external equipment's serial format? |
| A. | key matrix |
| B. | UART |
| C. | memory chip |
| D. | series in, parallel out |
| Answer» C. memory chip | |
| 97. |
Assume a LOW logic level is placed on the SHIFT/LOAD input of a 74195 shift register. The output will change ________. |
| A. | immediately |
| B. | if the CLOCK is also LOW |
| C. | on the next clock leading edge |
| D. | depending on the J and K inputs |
| Answer» D. depending on the J and K inputs | |
| 98. |
If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse? |
| A. | 1101000000 |
| B. | 11010000 |
| C. | 1100000000 |
| D. | 0 |
| Answer» C. 1100000000 | |
| 99. |
On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 = 1, Q2 = 1, and Q3 = 1. On the sixth clock pulse, the sequence is ________. |
| A. | Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0 |
| B. | Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 0 |
| C. | Q0 = 0, Q1 = 0, Q2 = 1, Q3 = 1 |
| D. | Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 1 |
| Answer» D. Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 1 | |