 
			 
			MCQOPTIONS
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				This section includes 7 Mcqs, each offering curated multiple-choice questions to sharpen your Vlsi knowledge and support exam preparation. Choose a topic below to get started.
| 1. | Rise time and fall time can be equalized by | 
| A. | n = p | 
| B. | n = 2 p | 
| C. | p = 2 n | 
| D. | n = 1/2 p | 
| Answer» B. n = 2 p | |
| 2. | Load capacitance can be minimized by | 
| A. | increasing A | 
| B. | decreasing A | 
| C. | increasing Psd | 
| D. | does not depend on A | 
| Answer» C. increasing Psd | |
| 3. | Switching power dissipation can be given as | 
| A. | Cl x Vdd x f | 
| B. | Vdd<sup>2</sup> x f | 
| C. | Cl x Vdd<sup>2</sup> | 
| D. | Cl x Vdd<sup>2</sup> x f | 
| Answer» E. | |
| 4. | For a regular 8:1 inverter, the transition delay is given as | 
| A. | 10 | 
| B. | 20 | 
| C. | 21 | 
| D. | 25 | 
| Answer» D. 25 | |
| 5. | In minimum size nMOS 8:1 inverter, the logic 1 to 0 transition delay is given as | 
| A. | 5 | 
| B. | 20 | 
| C. | 40 | 
| D. | 50 | 
| Answer» B. 20 | |
| 6. | In minimum size nMOS 8:1 inverter, the logic 0 to 1 transition delay is given as | 
| A. | 5 | 
| B. | 20 | 
| C. | 40 | 
| D. | 50 | 
| Answer» D. 50 | |
| 7. | When does the longest delay occur in 8:1 inverters? | 
| A. | during 1 to 0 transition | 
| B. | during 0 to 1 transition | 
| C. | during faster speed | 
| D. | delays are always short | 
| Answer» C. during faster speed | |