43 + Mcqs in Flip-Flops Page 1 McqOptions

1.	A gated S-R flip-flop goes into the SET condition when is HIGH, is LOW, and is HIGH.
A.	True
B.	False
Answer» B. False

Discussion

2.	VHDL require a special designation for an output with a feedback.
A.	True
B.	False
Answer» B. False

Discussion

3.	The term CLEAR always means that .
A.	True
B.	False
Answer» B. False

Discussion

4.	What does the triangle on the clock input of a flip-flop mean?
A.	level enabled
B.	edge-triggered
Answer» C.

Discussion

5.	The toggle condition in a master-slave flip-flop means that and will switch to their ________ state(s) at the ________.
A.	opposite, active clock edge
B.	inverted, positive clock edge
C.	quiescent, negative clock edge
D.	reset, synchronous clock edge
Answer» B. inverted, positive clock edge

Discussion

6.	An RC circuit used in a nonretriggerable 74121 one-shot has an Rof 49 k and a C of 0.2 F. The pulse width (t) is approximately ________.
A.	6.9
B.	s
C.	6.9 ms
D.	69 ms
E.	690 ms
Answer» C. 6.9 ms

Discussion

7.	With four flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?
A.	16
B.	8
C.	4
D.	2
Answer» C. 4

Discussion

8.	A 555 operating as a monostable multivibrator has a C = 0.01 F. Determine R for a pulse width of 2 ms.
A.	200 k
B.	182 k
C.	91 k
D.	182
Answer» C. 91 k

Discussion

9.	Why are the and inputs of a gated flip-flop said to be synchronous?
A.	They must occur with the gate.
B.	They occur independent of the gate.
Answer» B. They occur independent of the gate.

Discussion

10.	Gated flip-flops are called asynchronous because the output responds immediately to input changes.
A.	True
B.	False
Answer» C.

Discussion

11.	What is one disadvantage of an flip-flop?
A.	It has no enable input.
B.	It has an invalid state.
C.	It has no clock input.
D.	It has only a single output.
Answer» C. It has no clock input.

Discussion

12.	A correct output is achieved from a master-slave flip-flop only if its inputs are stable while the:
A.	clock is LOW
B.	slave is transferring
C.	flip-flop is reset
D.	clock is HIGH
Answer» E.

Discussion

13.	Which of the following describes the operation of a positive edge-triggered flip-flop?
A.	If both inputs are HIGH, the output will toggle.
B.	The output will follow the input on the leading edge of the clock.
C.	When both inputs are LOW, an invalid state exists.
D.	The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
Answer» C. When both inputs are LOW, an invalid state exists.

Discussion

14.	Master-slave flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.
A.	True
B.	False
Answer» C.

Discussion

15.	A 555 operating as a monostable multivibrator has a C = 100 F. Determine R for a pulse width of 500 ms.
A.	45
B.	455
C.	4.5 k
D.	455 k
Answer» D. 455 k

Discussion

16.	How can the cross-coupled NAND flip-flop be made to have active-HIGH inputs?
A.	It can't be done.
B.	Invert the Q outputs.
C.	Invert the
D.	inputs.
Answer» D. inputs.

Discussion

17.	A 555 operating as a monostable multivibrator has an R of 1 M. Determine C for a pulse width of 2 s.
A.	1.8
B.	F
C.	18 F
D.	18 pF
E.	18 nF
Answer» B. F

Discussion

18.	One example of the use of an flip-flop is as a(n):
A.	racer
B.	astable oscillator
C.	binary storage register
D.	transition pulse generator
Answer» D. transition pulse generator

Discussion

19.	Which of the following is correct for a gated flip-flop?
A.	The output toggles if one of the inputs is held HIGH.
B.	Only one of the inputs can be HIGH at a time.
C.	The output complement follows the input when enabled.
D.	output follows the input
E.	when the enable is HIGH.
Answer» E. when the enable is HIGH.

Discussion

20.	The output pulse width of a 555 monostable circuit with R = 4.7 k and C = 47 F is ________.
A.	24 s
B.	24 ms
C.	243 ms
D.	243
E.	s
Answer» D. 243

Discussion

21.	The output of a gated flip-flop changes only if the:
A.	flip-flop is set
B.	control input data has changed
C.	flip-flop is reset
D.	input data has no change
Answer» C. flip-flop is reset

Discussion

22.	For an flip-flop to be set or reset, the respective input must be:
A.	installed with steering diodes
B.	in parallel with a limiting resistor
C.	LOW
D.	HIGH
Answer» E.

Discussion

23.	The phenomenon of interpreting unwanted signals on and while (clock pulse) is HIGH is called ________.
A.	parity error checking
B.	ones catching
C.	digital discrimination
D.	digital filtering
Answer» C. digital discrimination

Discussion

24.	If both inputs of an flip-flop are LOW, what will happen when the clock goes high?
A.	No change will occur in the output.
B.	An invalid state will exist.
C.	The output will toggle.
D.	The output will reset.
Answer» B. An invalid state will exist.

Discussion

25.	Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (f) to the first flip-flop is 32 kHz, the output frequency (f) is ________.
A.	1 kHz
B.	2 kHz
C.	4 kHz
D.	16 kHz
Answer» C. 4 kHz

Discussion

26.	Propagation delay time, t, is measured from the ________.
A.	triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
B.	triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
C.	preset input to the LOW-to-HIGH transition of the output
D.	clear input to the HIGH-to-LOW transition of the output
Answer» B. triggering edge of the clock pulse to the HIGH-to-LOW transition of the output

Discussion

27.	The postponed symbol () on the output of a flip-flop identifies it as being ________.
A.	a D flip-flop
B.	a J-K flip-flop
C.	pulse triggered
D.	trailing edge-triggered
Answer» D. trailing edge-triggered

Discussion

28.	If data is brought into the terminal and its complement to the terminal, a J-K flip-flop operates as a(n) ________.
A.	S-C flip-flop
B.	D flip-flop
C.	gated S-C flip-flop
D.	TOGGLE flip-flop
Answer» C. gated S-C flip-flop

Discussion

29.	The point(s) on this timing diagram where the output of a D latch will be HIGH is/are ________.
A.	point 4
B.	points 3 and 4
C.	points 1 and 2
D.	points 4 and 5
Answer» B. points 3 and 4

Discussion

30.	The inputs on a 7474 D flip-flop are , , , and ________ is/are synchronous.
A.	Only
B.	and
C.	Only
D.	All of the above.
Answer» E.

Discussion

31.	A major drawback to an latch is its ________.
A.	complexity
B.	slow speed
C.	invalid condition
D.	latch mode
Answer» D. latch mode

Discussion

32.	The output of a flip-flop is normally HIGH when the device is in the "CLEAR" or "RESET" state.
A.	True
B.	False
Answer» C.

Discussion

33.	The 7475 is an example of an IC latch (also called a bistable latch) that contains four transparent latches.
A.	True
B.	False
Answer» B. False

Discussion

34.	The propagation delay time t is measured from the triggering edge of the clock pulse to the LOW-to-HIGH transition of the output.
A.	True
B.	False
Answer» B. False

Discussion

35.	Using knowledge from previous chapters, an flip-flop circuit is easy to design.
A.	True
B.	False
Answer» B. False

Discussion

36.	A D-type latch is able to change states and "follow" the input regardless of the level of the ENABLE input.
A.	True
B.	False
Answer» C.

Discussion

37.	When the output of the NOR gate S-R flip-flop is and , the inputs are .
A.	True
B.	False
Answer» C.

Discussion

38.	Edge-triggered flip-flops make it hard for design engineers to know when to accept input data.
A.	True
B.	False
Answer» C.

Discussion

39.	A TOGGLE input to a J-K flip-flop causes the and outputs to switch to their opposite state.
A.	True
B.	False
Answer» B. False

Discussion

40.	Pulse-triggered flip-flops are identified by a bubble on the output terminal.
A.	True
B.	False
Answer» C.

Discussion

41.	Simple gate circuits, combinational logic, and transparent flip-flops are synchronous.
A.	True
B.	False
Answer» C.

Discussion

42.	A flip-flop is in the CLEAR condition when .
A.	True
B.	False
Answer» C.

Discussion

43.	The gated flip-flop is asynchronous.
A.	True
B.	False
Answer» C.

Discussion

Explore topic-wise MCQs in Digital Electronics.

A gated S-R flip-flop goes into the SET condition when is HIGH, is LOW, and is HIGH.

VHDL require a special designation for an output with a feedback.

The term CLEAR always means that .

What does the triangle on the clock input of a flip-flop mean?

The toggle condition in a master-slave flip-flop means that and will switch to their ________ state(s) at the ________.

An RC circuit used in a nonretriggerable 74121 one-shot has an Rof 49 k and a C of 0.2 F. The pulse width (t) is approximately ________.

With four flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?

A 555 operating as a monostable multivibrator has a C = 0.01 F. Determine R for a pulse width of 2 ms.

Why are the and inputs of a gated flip-flop said to be synchronous?

Gated flip-flops are called asynchronous because the output responds immediately to input changes.

What is one disadvantage of an flip-flop?

A correct output is achieved from a master-slave flip-flop only if its inputs are stable while the:

Which of the following describes the operation of a positive edge-triggered flip-flop?

Master-slave flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.

A 555 operating as a monostable multivibrator has a C = 100 F. Determine R for a pulse width of 500 ms.

How can the cross-coupled NAND flip-flop be made to have active-HIGH inputs?

A 555 operating as a monostable multivibrator has an R of 1 M. Determine C for a pulse width of 2 s.

One example of the use of an flip-flop is as a(n):

Which of the following is correct for a gated flip-flop?

The output pulse width of a 555 monostable circuit with R = 4.7 k and C = 47 F is ________.

The output of a gated flip-flop changes only if the:

For an flip-flop to be set or reset, the respective input must be:

The phenomenon of interpreting unwanted signals on and while (clock pulse) is HIGH is called ________.

If both inputs of an flip-flop are LOW, what will happen when the clock goes high?

Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (f) to the first flip-flop is 32 kHz, the output frequency (f) is ________.

Propagation delay time, t, is measured from the ________.

The postponed symbol () on the output of a flip-flop identifies it as being ________.

If data is brought into the terminal and its complement to the terminal, a J-K flip-flop operates as a(n) ________.

The point(s) on this timing diagram where the output of a D latch will be HIGH is/are ________.

The inputs on a 7474 D flip-flop are , , , and ________ is/are synchronous.

A major drawback to an latch is its ________.

The output of a flip-flop is normally HIGH when the device is in the "CLEAR" or "RESET" state.

The 7475 is an example of an IC latch (also called a bistable latch) that contains four transparent latches.

The propagation delay time t is measured from the triggering edge of the clock pulse to the LOW-to-HIGH transition of the output.

Using knowledge from previous chapters, an flip-flop circuit is easy to design.

A D-type latch is able to change states and "follow" the input regardless of the level of the ENABLE input.

When the output of the NOR gate S-R flip-flop is and , the inputs are .

Edge-triggered flip-flops make it hard for design engineers to know when to accept input data.

A TOGGLE input to a J-K flip-flop causes the and outputs to switch to their opposite state.

Pulse-triggered flip-flops are identified by a bubble on the output terminal.

Simple gate circuits, combinational logic, and transparent flip-flops are synchronous.

A flip-flop is in the CLEAR condition when .

The gated flip-flop is asynchronous.

The toggle condition in a master-slave flip-flop means that and will switch to their state(s) at the .