96 + Mcqs in Digital System Projects Using Hdl Page 2 McqOptions

51.	A very critical dimension in project management is ________.
A.	cost
B.	skill
C.	time
D.	personnel
Answer» D. personnel

Discussion

52.	In the digital clock project, what is the frequency of the MOD-6 counter in the minutes section?
A.	1 pulse per minute
B.	6 pulses per minute
C.	10 pulses per minute
D.	1 pulse per hour
Answer» E.

Discussion

53.	The interface of the stepper motor needs to operate in one of ________ mode(s).
A.	one
B.	two
C.	three
D.	four
Answer» E.

Discussion

54.	The frequency counter measures frequency by enabling a counter to count the number of pulses of the incoming waveform during a precisely specified period of time called the sampling time.
A.	1
B.
Answer» C.

Discussion

55.	What does the ring counter in the HDL keypad application do when a key is pressed?
A.	Count to find the row
B.	Freeze
C.	Count to find the column
D.	Start the D flip-flop
Answer» C. Count to find the column

Discussion

56.	In the frequency counter, when is the new count stored in the display register?
A.	After disabling the counter
B.	When the count buffer is full
C.	After the sample interval is set
D.	When the timing and control block has put it there
Answer» B. When the count buffer is full

Discussion

57.	The accuracy of the frequency counter depends on the:
A.	system clock frequency.
B.	number of displayed digits.
C.	sampling rate.
D.	display update rate.
Answer» B. number of displayed digits.

Discussion

58.	In the keypad application, just after the 4 ms mark the simulation imitates the release of the key by changing the column value back to F hex, which causes the d output to go into its Hi-Z state. On the next rising clock edge, what happens to dav?
A.	It goes HIGH.
B.	It goes LOW.
C.	It goes to Hi-Z.
D.	It goes to 1111H.
Answer» C. It goes to Hi-Z.

Discussion

59.	When designing an HDL digital system, which is the worst mistake one can make?
A.	Concluding that a fundamental block works perfectly
B.	Failing to provide proper documentation
C.	Adding blocks of code prior to testing them
D.	Overlooking a possible VARIABLE
Answer» B. Failing to provide proper documentation

Discussion

60.	One of the first steps in any HDL project is to define its scope by naming each input and output.
A.	1
B.
C.	1
D.
Answer» B.

Discussion

61.	A frequency counter ________ a signal.
A.	measures
B.	displays
C.	measures and displays
D.	measures, displays, and generates
Answer» D. measures, displays, and generates

Discussion

62.	In the keypad encoder, the ________ must hold in its current state until a key is released.
A.	ring counter
B.	MOD-6 counter
C.	BCD counter
D.	freeze bit
Answer» B. MOD-6 counter

Discussion

63.	The timing and control block provides the ________ for the frequency counter.
A.	brains
B.	BCD counters
C.	display register
D.	six different frequency measurement ranges
Answer» B. BCD counters

Discussion

64.	In the digital clock project, the 60 Hz signal is sent through a Schmitt-trigger circuit to produce square pulses at the rate of ________.
A.	1 pps
B.	60 pps
C.	100 pps
D.	600 pps
Answer» C. 100 pps

Discussion

65.	What are two ways to remember the current state of a counter in VHDL?
A.	With FUNCTIONS and PROCESS
B.	With counters and timers
C.	With SIGNAL and VARIABLE
D.	With bit types
Answer» D. With bit types

Discussion

66.	What does the major block of an HDL code emulation of a keypad include?
A.	A sequencer
B.	A clock
C.	A multiplexer
D.	A ring counter
Answer» E.

Discussion

67.	Which is not a major block of an HDL frequency counter?
A.	Display register
B.	Decoder/display
C.	Timing and control unit
D.	Bit shifter
Answer» E.

Discussion

68.	In the keypad application, when all columns are HIGH, the ring counter is enabled and counting, and dav is LOW, what is the status of the d outputs?
A.	On
B.	Off
C.	Hi-Z
D.	1011
Answer» D. 1011

Discussion

69.	Which is not a step that should be followed in project management?
A.	Overall definition
B.	System documentation
C.	Synthesis and testing
D.	System integration
Answer» C. Synthesis and testing

Discussion

70.	In the digital clock project, frequency prescaling is used to take a 1 pps input and transform it into a 60 pps timing signal.
A.	1
B.
Answer» C.

Discussion

71.	In HDL, one of the strategies used in strategic planning is to find the speed requirements.
A.	1
B.
C.	1
D.
Answer» C. 1

Discussion

72.	One of the first steps in any HDL project is to define its scope by knowing the nature of all the signals that are interconnected to pieces of the project.
A.	1
B.
Answer» C.

Discussion

73.	In the digital clock project HDL code, the MOD-12 counter is using ________.
A.	a BCD counter followed by a MOD-2 counter
B.	a single HDL module
C.	a MOD-6 counter followed by a MOD-2 counter
D.	a MOD-12 counter followed by a D flip-flop
Answer» C. a MOD-6 counter followed by a MOD-2 counter

Discussion

74.	List three basic blocks in the digital clock project.
A.	MOD-60, MOD-12 counters
B.	MOD-5, MOD-10, MOD-12 counters
C.	MOD-60, MOD-10 counters
D.	MOD-6, MOD-12, and MOD-10 counters
Answer» E.

Discussion

75.	The half-step sequence of a stepper motor is created by inserting a start with only one coil energized between full steps.
A.	1
B.
Answer» B.

Discussion

76.	In the frequency counter, if the clock generator produces a 100 kHz system clock signal, how many decade counters are required to measure 1 Hz?
A.	6
B.	5
C.	4
D.	3
Answer» C. 4

Discussion

77.	In the digital clock project, a MOD-60 BCD counter is made from a MOD-10 counter cascaded to a MOD-6 BCD counter.
A.	1
B.
C.	1
D.
Answer» B.

Discussion

78.	In the digital clock project, what type of counter is used to count to 59 seconds?
A.	MOD-60
B.	MOD-6
C.	BCD
D.	BCD followed by a MOD-6
Answer» E.

Discussion

79.	In a full-step sequence involving two flip-flops driving four coils of a stepper motor, how far will the stepper motor step?
A.	90¬∞
B.	45¬∞
C.	30¬∞
D.	15¬∞
Answer» E.

Discussion

80.	In the keypad encoder, the ring counter is implemented using ________ that responds to the clk input.
A.	SIGNAL
B.	FUNCTION
C.	CASE
D.	PROCESS
Answer» E.

Discussion

81.	In the digital clock project, the purpose of the frequency prescaler is to:
A.	find the basic frequency.
B.	transform a 60 pps input to a 1 pps timing signal.
C.	prevent the clock from exceeding 12:59:59.
D.	allow the BCD display to have a value from 00‚Äì59.
Answer» C. prevent the clock from exceeding 12:59:59.

Discussion

82.	In the keypad application, what does the preset state of the ring counter define?
A.	The proper output of the column encoder
B.	The NANDing of the rows
C.	The NANDing of the columns
D.	The proper output of the row encoder
Answer» E.

Discussion

83.	For the frequency counter, which is not a control signal from the control and timing block?
A.	Clear
B.	Enable
C.	Reset
D.	Store
Answer» D. Store

Discussion

84.	In HDL, one of the strategies used in strategic planning is to find a way to test each piece of the project.
A.	1
B.
C.	1
D.
Answer» B.

Discussion

85.	In the digital clock project, when does the PM indicator go high?
A.	Never
B.	Going from 11:59:59 to 12:00:00
C.	Going from 12:59:59 to 01:00:00
D.	On the falling edge of the clock after enable goes high
Answer» C. Going from 12:59:59 to 01:00:00

Discussion

86.	In an HDL stepper motor design, why is there more than one mode?
A.	To change the speed of the stepper motor
B.	To change the direction of the stepper motor
C.	To direct drive the stepper motor
D.	All of the above
Answer» E.

Discussion

87.	Top-down design means that we start at the highest level of the hierarchy, or that the entire project is considered to exist in a closed dark box with inputs and outputs.
A.	1
B.
C.	1
D.
Answer» B.

Discussion

88.	In the digital clock project, the 1 pps signal is used as a synchronous clock for all of the counter stages, which are ________.
A.	advanced BCD counters
B.	MOD-6 counters
C.	synchronous cascaded
D.	1 pulse per second
Answer» D. 1 pulse per second

Discussion

89.	In the keypad application, what does the data signal define?
A.	The row and column encoded data
B.	The ring encoded data
C.	The freeze locator data
D.	The ring counter data
Answer» B. The ring encoded data

Discussion

90.	In the frequency counter, what is the function of the Schmitt trigger circuit?
A.	To reduce input noise
B.	To condition the input signal
C.	To convert non-square waveforms
D.	To provide a usable signal to the display unit
Answer» D. To provide a usable signal to the display unit

Discussion

91.	In an HDL application of a stepper motor, after an up/down counter is built what is done next?
A.	Build the sequencer
B.	Test it on a simulator
C.	Test the decoder
D.	Design an intermediate integer variable
Answer» C. Test the decoder

Discussion

92.	How is the output frequency related to the sampling interval of a frequency counter?
A.	Directly with the sampling interval
B.	Inversely with the sampling interval
C.	More precision with longer sampling interval
D.	Less precision with longer sampling interval
Answer» D. Less precision with longer sampling interval

Discussion

93.	Which is not a step in strategic planning for HDL development?
A.	There must be a way to test each piece.
B.	Each block must fit together to make up the whole system.
C.	The names of each input and output must be known.
D.	The exact operation of each block must be thoroughly defined and understood.
Answer» D. The exact operation of each block must be thoroughly defined and understood.

Discussion

94.	Why should a real hardware functional test be performed on the HDL stepper motor design?
A.	To check the speed of the software
B.	To check the current levels in the motor
C.	To check the voltage levels of the real outputs
D.	To provide a fully operational system
Answer» B. To check the current levels in the motor

Discussion

95.	In a digital clock application, the basic frequency must be divided down to:
A.	1 Hz.
B.	60 Hz.
C.	100 Hz.
D.	1000 Hz.
Answer» B. 60 Hz.

Discussion

96.	In a frequency counter, what happens at high frequencies when the sampling interval is too long?
A.	The counter works fine.
B.	The counter undercounts the frequency.
C.	The measurement is less precise.
D.	The counter overflows.
Answer» E.

Discussion

Explore topic-wise MCQs in Digital Electronics.

A very critical dimension in project management is ________.

In the digital clock project, what is the frequency of the MOD-6 counter in the minutes section?

The interface of the stepper motor needs to operate in one of ________ mode(s).

The frequency counter measures frequency by enabling a counter to count the number of pulses of the incoming waveform during a precisely specified period of time called the sampling time.

What does the ring counter in the HDL keypad application do when a key is pressed?

In the frequency counter, when is the new count stored in the display register?

The accuracy of the frequency counter depends on the:

In the keypad application, just after the 4 ms mark the simulation imitates the release of the key by changing the column value back to F hex, which causes the d output to go into its Hi-Z state. On the next rising clock edge, what happens to dav?

When designing an HDL digital system, which is the worst mistake one can make?

One of the first steps in any HDL project is to define its scope by naming each input and output.

A frequency counter ________ a signal.

In the keypad encoder, the ________ must hold in its current state until a key is released.

The timing and control block provides the ________ for the frequency counter.

In the digital clock project, the 60 Hz signal is sent through a Schmitt-trigger circuit to produce square pulses at the rate of ________.

What are two ways to remember the current state of a counter in VHDL?

What does the major block of an HDL code emulation of a keypad include?

Which is not a major block of an HDL frequency counter?

In the keypad application, when all columns are HIGH, the ring counter is enabled and counting, and dav is LOW, what is the status of the d outputs?

Which is not a step that should be followed in project management?

In the digital clock project, frequency prescaling is used to take a 1 pps input and transform it into a 60 pps timing signal.

In HDL, one of the strategies used in strategic planning is to find the speed requirements.

One of the first steps in any HDL project is to define its scope by knowing the nature of all the signals that are interconnected to pieces of the project.

In the digital clock project HDL code, the MOD-12 counter is using ________.

List three basic blocks in the digital clock project.

The half-step sequence of a stepper motor is created by inserting a start with only one coil energized between full steps.

In the frequency counter, if the clock generator produces a 100 kHz system clock signal, how many decade counters are required to measure 1 Hz?

In the digital clock project, a MOD-60 BCD counter is made from a MOD-10 counter cascaded to a MOD-6 BCD counter.

In the digital clock project, what type of counter is used to count to 59 seconds?

In a full-step sequence involving two flip-flops driving four coils of a stepper motor, how far will the stepper motor step?

In the keypad encoder, the ring counter is implemented using ________ that responds to the clk input.

In the digital clock project, the purpose of the frequency prescaler is to:

In the keypad application, what does the preset state of the ring counter define?

For the frequency counter, which is not a control signal from the control and timing block?

In HDL, one of the strategies used in strategic planning is to find a way to test each piece of the project.

In the digital clock project, when does the PM indicator go high?

In an HDL stepper motor design, why is there more than one mode?

Top-down design means that we start at the highest level of the hierarchy, or that the entire project is considered to exist in a closed dark box with inputs and outputs.

In the digital clock project, the 1 pps signal is used as a synchronous clock for all of the counter stages, which are ________.

In the keypad application, what does the data signal define?

In the frequency counter, what is the function of the Schmitt trigger circuit?

In an HDL application of a stepper motor, after an up/down counter is built what is done next?

How is the output frequency related to the sampling interval of a frequency counter?

Which is not a step in strategic planning for HDL development?

Why should a real hardware functional test be performed on the HDL stepper motor design?

In a digital clock application, the basic frequency must be divided down to:

In a frequency counter, what happens at high frequencies when the sampling interval is too long?