MCQOPTIONS
Saved Bookmarks
MCQOPTIONS
This section includes 289 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Electronics knowledge and support exam preparation. Choose a topic below to get started.
| 201. |
With reference to the exclusive OR gate with many inputs, consider the following statements |
| A. | 1, 2 |
| B. | 3, 4 |
| C. | 1, 3 |
| D. | 2, 4 |
| Answer» B. 3, 4 | |
| 202. |
Simplify (X + Y) (X + |
| A. | X |
| B. | Y |
| C. | X + X |
| D. | <span style="text-decoration:overline">Y</span> |
| E. | X (1 + Y) |
| Answer» B. Y | |
| 203. |
Find output of given circuit |
| A. | f = AB + BCD |
| B. | f = A(B + C + D) |
| C. | f = AC + BCD |
| D. | f = AB + AC + BCD |
| Answer» E. | |
| 204. |
The Boolean expression A + |
| A. | Sum term |
| B. | A literal term |
| C. | A product term |
| D. | A complement term |
| Answer» E. | |
| 205. |
Which of the following rules state that if one input of an AND gate is always 1, the output is equal to the other input? |
| A. | A + 1 = 1 |
| B. | A + A = A |
| C. | A A = A |
| D. | A 1 = A |
| Answer» E. | |
| 206. |
The domain of expression A |
| A. | A and D |
| B. | B only |
| C. | A, B, C, D |
| D. | None of these |
| Answer» C. A, B, C, D | |
| 207. |
The Boolean expression A |
| A. | Sum term |
| B. | Product term |
| C. | A literal term |
| D. | Always 1 |
| Answer» B. Product term | |
| 208. |
In given fig. if A = 1 and B = 0, Y will be |
| A. | 0 |
| B. | 1 |
| C. | 0 or 1 |
| D. | None of these |
| Answer» B. 1 | |
| 209. |
What will be the data in shift register after four clock pulses? |
| A. | 0000 |
| B. | 0101 |
| C. | 1010 |
| D. | 1111 |
| Answer» D. 1111 | |
| 210. |
Which of the following measurements can be done using a counter? |
| A. | 1 and 2 |
| B. | 2 and 3 |
| C. | 1 and 4 |
| D. | 2 and 4 |
| Answer» B. 2 and 3 | |
| 211. |
How many words are in the truth table of above fig.? |
| A. | 2 |
| B. | 4 |
| C. | 8 |
| D. | 16 |
| Answer» E. | |
| 212. |
Number of NAND gates are required to realize the function |
| A. | 3 |
| B. | 4 |
| C. | 5 |
| D. | 6 |
| Answer» C. 5 | |
| 213. |
Which of the following capabilities are available in a Universal Shift Register? |
| A. | 2 and 4 only |
| B. | 1, 2 and 3 |
| C. | 1, 2 and 4 |
| D. | 1, 3 and 4 |
| Answer» C. 1, 2 and 4 | |
| 214. |
Determine the values of A, B, C, D that make the product term AB CD equal to 1 |
| A. | A = 0, B = 1, C = 0, D = 1 |
| B. | A = 0, B = 1, C = 1, D = 1 |
| C. | A = 1, B = 1, C = 1, D = 0 |
| D. | A = 1, B = 0, C = 0, D = 0 |
| Answer» B. A = 0, B = 1, C = 1, D = 1 | |
| 215. |
Consider the following statements regarding registers and latches: |
| A. | 1 only |
| B. | 1 and 3 |
| C. | 2 and 3 |
| D. | 3 and 4 |
| Answer» C. 2 and 3 | |
| 216. |
A pulse is applied to each input of a 2 input NAND gate. One pulse goes HIGH at t = 0 and goes back low at t = 1 ms. The other pulse goes HIGH at t = 0 8 ms and goes back low at t = 3 ms. The output pulse can be described as follows |
| A. | It goes LOW at t = 0 and back HIGH at t = 3 ms |
| B. | It goes LOW at t = 0 8 ms and back HIGH at t = 3 ms |
| C. | It goes LOW at t = 0 8 ms and back HIGH at t = 1 ms |
| D. | It goes LOW at t = 0 8 ms and back LOW at t = 1 ms |
| Answer» D. It goes LOW at t = 0 8 ms and back LOW at t = 1 ms | |
| 217. |
The shift register shown below is initially loaded with the bit pattern 1010. Subsequently the shift register is clocked, and with each clock pulse the pattern gets shifted by one bit position to the right. With each shift, the bit at the serial input is pushed to the left most position (i.e. MSB). After how many clock pulses will the content of the shift register become 1010 again |
| A. | 3 |
| B. | 7 |
| C. | 11 |
| D. | 15 |
| Answer» C. 11 | |
| 218. |
Shifting a register to the left by one bit position is equivalent to (in binary code) |
| A. | Division by 2 |
| B. | Multiplication by 2 |
| C. | Addition of 2 |
| D. | Subtraction of 2 |
| Answer» C. Addition of 2 | |
| 219. |
For the logic circuit given. Which is the simplified Boolean function? |
| A. | X = AB + C |
| B. | X = B + A |
| C. | X = AB + AC |
| D. | X = AC + B |
| Answer» C. X = AB + AC | |
| 220. |
The binary number 110011 is to be converted to Gray code. The number of gates and type required are |
| A. | 6, AND |
| B. | 6, XNOR |
| C. | 6, XOR |
| D. | 5, XOR |
| Answer» E. | |
| 221. |
For the figure given below |
| A. | Y = + 255 |
| B. | Y = + 127 |
| C. | Y = + 31 |
| D. | Y = 0 |
| Answer» C. Y = + 31 | |
| 222. |
If the input to the digital circuit shown below, consisting of a cascade of 20 EX-OR gates is X. Then the output Y is equal to 1 X Y |
| A. | 0 |
| B. | 1 |
| C. | <span style="text-decoration:overline">X</span> |
| D. | X |
| Answer» C. <span style="text-decoration:overline">X</span> | |
| 223. |
The output of the logic gate in the given figure is |
| A. | Y = 0 |
| B. | Y = 1 |
| C. | Y = A |
| D. | Y = |
| E. | <span style="text-decoration:overline">A</span> |
| Answer» E. <span style="text-decoration:overline">A</span> | |
| 224. |
Assume that only the X and Y logic inputs are available and their complements |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» D. 5 | |
| 225. |
A cascade arrangement of four stages of BCD counters can be used to count a maximum of |
| A. | 1111 pulses |
| B. | 111111111111111 pulses |
| C. | 1001100110011001 pulses |
| D. | 9999 pulses |
| Answer» E. | |
| 226. |
A five-bit Johnson counter in cascade with a five-bit ring counter produces a frequency divider of |
| A. | 25 |
| B. | 10 |
| C. | 50 |
| D. | 15 |
| Answer» D. 15 | |
| 227. |
The following configuration provides |
| A. | Master Slave action |
| B. | Delay gate |
| C. | Toggle switch |
| D. | None of these |
| Answer» D. None of these | |
| 228. |
Sequential circuits contains |
| A. | No memory element |
| B. | Atleast one memory element |
| C. | All inputs applied simultaneously |
| D. | None of these |
| Answer» C. All inputs applied simultaneously | |
| 229. |
In sequential circuit the output state depend upon |
| A. | Past input states |
| B. | Present input states |
| C. | Present as well as past input |
| D. | None of these |
| Answer» D. None of these | |
| 230. |
The problem of decoding glitches can be taken care of |
| A. | By using flip-flops with equal propagation delays |
| B. | By using a strobing signal |
| C. | By using flip-flops with unequal propagation delays |
| D. | By using J-K flip-flop instead of D-flip-flops |
| Answer» C. By using flip-flops with unequal propagation delays | |
| 231. |
The decoding glitches are more likely to occur in the case of |
| A. | Ripple counters |
| B. | Parallel counters |
| C. | Johnson counters |
| D. | Ring counters |
| Answer» B. Parallel counters | |
| 232. |
The minimum number of flip-flops required to construct a MOD-10 Johnson counter and MOD 5 ring counter, respectively, are |
| A. | 10, 5 |
| B. | 5, 10 |
| C. | 5, 5 |
| D. | 10, 10 |
| Answer» D. 10, 10 | |
| 233. |
An octal D flip-flop IC can be used to construct a |
| A. | MOD-8 ring counter |
| B. | MOD-16 ring counter |
| C. | MOD-32 Johnson counter |
| D. | Both (A) and (B) |
| Answer» E. | |
| 234. |
Consider the following statements in Johnson counter: |
| A. | 1 and 2 |
| B. | 2 and 3 |
| C. | 1 and 3 |
| D. | 1, 2 and 3 |
| Answer» E. | |
| 235. |
A shift counter comprising five flip-flops with an inverse feedback from the output of the MSB flip-flop to the input of the LSB flip-flops is a |
| A. | Divide-by-32 counter |
| B. | Divide-by-10 counter |
| C. | Divide-by-5 counter |
| D. | Five-bit shift register |
| Answer» C. Divide-by-5 counter | |
| 236. |
The minimum number of flip-flops needed to construct a BCD decade counter is |
| A. | 4 |
| B. | 3 |
| C. | 10 |
| D. | None of these |
| Answer» B. 3 | |
| 237. |
The circuit given below illustrates a typical application of the JK flip-flop. What does this represent? |
| A. | A shift register |
| B. | A data storage device |
| C. | A frequency divider circuit |
| D. | A decoder circuit |
| Answer» D. A decoder circuit | |
| 238. |
A four-bit binary UP-DOWN counter is initially reset to 0000. The UP/DOWN mode select terminal designated as U/D on the pin connection diagram of the IC is tied to logic HIGH level. What would be the counter s output state at the end of the first clock pulse? |
| A. | 0001 |
| B. | 1000 |
| C. | 1111 |
| D. | 0000 |
| Answer» D. 0000 | |
| 239. |
A 10 kHz clock signal having a duty cycle of 25% is used to clock a three-bit binary ripple counter. What will be the frequency and duty cycle of the true output of the MSB flip-flop? |
| A. | 1.25 kHz, 25% |
| B. | 1.25 kHz, 50% |
| C. | 3.33 kHz, 25% |
| D. | 3.33 kHz, 50% |
| Answer» C. 3.33 kHz, 25% | |
| 240. |
All BCD counters |
| A. | Are decade counters because all decade counters are BCD counters |
| B. | Are not decade counter |
| C. | Have a modulus of 10 |
| D. | Are constructed with only present table D flip-flops |
| E. | Both (C) and (D) are correct |
| Answer» D. Are constructed with only present table D flip-flops | |
| 241. |
In any asynchronous counter |
| A. | All flip-flops change state at the same time |
| B. | Only D flip-flops are used |
| C. | The counter responds to negative going clock edges |
| D. | Each flip-flop output serves as clock input to the next flip-flop |
| Answer» E. | |
| 242. |
In what type of shift register do we have access to only the leftmost and rightmost flip-flops |
| A. | Serial-in/serial-out shift register |
| B. | Serial-in/parallel-output shift register |
| C. | Parallel-in/serial-out shift register |
| D. | Parallel-in/parallel-out shift register |
| Answer» B. Serial-in/parallel-output shift register | |
| 243. |
Mark the false statement |
| A. | Ring counter is a synchronous counter |
| B. | Johnson counter is a synchronous counter |
| C. | The output of a ring counter is always a square wave |
| D. | The decoding circuitry for a Johnson counter is simpler than that of a binary counter |
| Answer» D. The decoding circuitry for a Johnson counter is simpler than that of a binary counter | |
| 244. |
A MOD-32 binary synchronous counter would require |
| A. | 6 flip-flops and 3 NAND gates |
| B. | 5 flip-flops |
| C. | 5 flip-flops and 3 AND gates |
| D. | None of these |
| Answer» D. None of these | |
| 245. |
A binary ripple counter is to be constructed using J-K flip-flops with each flip-flop having a propagation delay of 12 ns. The largest MOD counter that can be constructed using these flip-flops and still operate upto a clock frequency of 10 MHz is |
| A. | MOD-16 |
| B. | MOD-64 |
| C. | MOD-256 |
| D. | MOD-8 |
| Answer» D. MOD-8 | |
| 246. |
A counter that has a modulus of 64 should use a minimum of |
| A. | 6 flip-flops |
| B. | 6 J-K type flip-flops |
| C. | 6 D flip-flops |
| D. | 64 flip-flops |
| Answer» B. 6 J-K type flip-flops | |
| 247. |
For given MOD-16 counter with a 10 MHz clock input. Determine the frequency at Q3 |
| A. | 625 kHz |
| B. | 62.5 kHz |
| C. | 10 MHz |
| D. | 5 MHz |
| Answer» B. 62.5 kHz | |
| 248. |
A certain JK flip-flop has tpd = 12 n sec. What is the largest MOD counter, that can be constructed from these FFs and still operate upto 10 MHz? |
| A. | 16 |
| B. | 64 |
| C. | 128 |
| D. | 256 |
| Answer» E. | |
| 249. |
The counter starts off in the '0000' state, and then clock pulses are applied. Some time later the clock pulses are removed and the counter FFs read '0011'. How many clock pulses have occurred? |
| A. | 3 |
| B. | 35 |
| C. | 51 |
| D. | Any of them |
| Answer» E. | |
| 250. |
Assume that counter is holding the count 0101. What will be the count after 27 clock pulses? |
| A. | 0101 |
| B. | 0001 |
| C. | 1111 |
| D. | 0000 |
| Answer» E. | |