MCQOPTIONS
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MCQOPTIONS
This section includes 19 Mcqs, each offering curated multiple-choice questions to sharpen your Vlsi knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
The circuits with poor observability are: |
| A. | ROM |
| B. | PLA |
| C. | Sequential circuits with long feedback loops |
| D. | All of the mentioned |
| Answer» D. All of the mentioned | |
| 2. |
The poor controllability circuits are: |
| A. | Decoders |
| B. | Clock generators |
| C. | Circuits with feedback |
| D. | All of the mentioned |
| Answer» E. | |
| 3. |
The ease with which the controller determines signal value at any node by setting input values is known as: |
| A. | Testability |
| B. | Observability |
| C. | Controllability |
| D. | Manufacturability |
| Answer» C. Controllability | |
| 4. |
The ease with which the controller establishes specific signal value at each node by setting input values is known as: |
| A. | Testability |
| B. | Observability |
| C. | Controllability |
| D. | Manufacturability |
| Answer» D. Manufacturability | |
| 5. |
The defect present in the following MOSFET is: |
| A. | Logical stuck at 1 |
| B. | Logical stuck at 0 |
| C. | Physical defect |
| D. | Electrical Transistor stuck open |
| Answer» E. | |
| 6. |
THE_EASE_WITH_WHICH_THE_CONTROLLER_DETERMINES_SIGNAL_VALUE_AT_ANY_NODE_BY_SETTING_INPUT_VALUES_IS_KNOWN_AS:?$ |
| A. | Testability |
| B. | Observability |
| C. | Controllability |
| D. | Manufacturability |
| Answer» C. Controllability | |
| 7. |
The circuits with poor observability are:$ |
| A. | ROM |
| B. | PLA |
| C. | Sequential circuits with long feedback loops |
| D. | All of the mentioned |
| Answer» D. All of the mentioned | |
| 8. |
The poor controllability circuits are:$ |
| A. | Decoders |
| B. | Clock generators |
| C. | Circuits with feedback |
| D. | All of the mentioned |
| Answer» E. | |
| 9. |
LSSD stands for: |
| A. | Linear system synchronous detection |
| B. | Level sensitive system detection |
| C. | Level sensitive scan design |
| D. | Level sensitive scan detection |
| Answer» D. Level sensitive scan detection | |
| 10. |
Divide and Conquer approach to large and complex circuits for testing is found in: |
| A. | Partition and Mux Technique |
| B. | Simplified automatic test pattern generation technique |
| C. | Scan based technique |
| D. | All of the mentioned |
| Answer» B. Simplified automatic test pattern generation technique | |
| 11. |
Large number of input vectors are used to set a particular node (1) or (0), to propagate an error at the node to output makes the circuit low on: |
| A. | Testability |
| B. | Observability |
| C. | Controllability |
| D. | All of the mentioned |
| Answer» B. Observability | |
| 12. |
The ease with which the controller establish specific signal value at each node by setting input values is known as? |
| A. | Testability |
| B. | Observability |
| C. | Controllability |
| D. | Manufacturability |
| Answer» D. Manufacturability | |
| 13. |
The fault simulation detects faults by: |
| A. | Test generation |
| B. | Construction of fault Dictionaries |
| C. | Design analysis under faults |
| D. | All of the mentioned |
| Answer» E. | |
| 14. |
High resistance short present between drain and ground of n-MOSFET inverter acts as: |
| A. | Pull up delay error |
| B. | Logical fault as output is stuck at 1 |
| C. | Electrical fault as transistor stuck on |
| D. | All of the mentioned |
| Answer» B. Logical fault as output is stuck at 1 | |
| 15. |
A metallic blob present between drain and the ground of the n-MOSFET inverter acts as: |
| A. | Physical defect |
| B. | Logical fault as output is stuck on 0 |
| C. | Electrical fault as resistor short |
| D. | All of the mentioned |
| Answer» E. | |
| 16. |
Delay fault is considered as: |
| A. | Electrical fault |
| B. | Logical fault |
| C. | Physical defect |
| D. | None of the Mentioned |
| Answer» C. Physical defect | |
| 17. |
ATPG stands for: |
| A. | Attenuated Transverse wave Pattern Generation |
| B. | Automatic Test Pattern Generator |
| C. | Aligned Test Parity Generator |
| D. | None of the mentioned |
| Answer» C. Aligned Test Parity Generator | |
| 18. |
The functions performed during chip testing are: |
| A. | Detect faults in fabrication. |
| B. | Detect faults in design |
| C. | Failures in functionality |
| D. | All of the mentioned |
| Answer» E. | |
| 19. |
Design for testability is considered in production for chips because: |
| A. | Manufactured chips are faulty and are required to be tested |
| B. | The design of chips are required to be tested |
| C. | Many chips are required to be tested within short interval of time which yields timely delivery for the customers. |
| D. | All of the mentioned |
| Answer» D. All of the mentioned | |