190 + Mcqs in Counters Page 1 McqOptions

1.	A MOD-16 ripple counter is holding the count 1001. What will the count be after 31 clock pulses?
A.	1000
B.	1010
C.	1011
D.	1101
Answer» B. 1010

Discussion

2.	After 10 clock cycles, and assuming that the DATA input had returned to 0 following the storage sequence, what values would be stored in 4, 3, 2, 1, 0 of the register in Figure 7-5?
A.	0,1,0,1,1
B.	1,1,0,1,0
C.	1,0,1,0,1
D.	0,0,0,0,0
Answer» E.

Discussion

3.	A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (t) is ________.
A.	12 ms
B.	24 ns
C.	48 ns
D.	60 ns
Answer» E.

Discussion

4.	Any divide-by- counter can be formed by using external gating to ________ at a predetermined number.
A.	HIGH
B.	reset
C.	LOW
D.	preset
Answer» C. LOW

Discussion

5.	The designation means that the ________.
A.	up count is active-HIGH, the down count is active-LOW
B.	up count is active-LOW, the down count is active-HIGH
C.	up and down counts are both active-LOW
D.	up and down counts are both active-HIGH
Answer» B. up count is active-LOW, the down count is active-HIGH

Discussion

6.	What is the maximum delay that can occur if four flip-flops are connected as a ripple counter and each flip-flop has propagation delays of = 22 ns and = 15 ns?
A.	15 ns
B.	22 ns
C.	60 ns
D.	88 ns
Answer» E.

Discussion

7.	The term refers to events that do not occur at the same time.
A.	True
B.	False
Answer» C.

Discussion

8.	The term , as applied to counter operations, means that the counter is clocked such that each flip-flop in the counter is triggered at the same time.
A.	True
B.	False
Answer» B. False

Discussion

9.	A J-K flip-flop excitation table lists the present state, the next state, and the and levels required to produce each transition.
A.	True
B.	False
Answer» B. False

Discussion

10.	A parallel in/serial out shift register enters all data bits simultaneously and transfers them out one bit at a time.
A.	True
B.	False
Answer» B. False

Discussion

11.	Another term used to describe up/down counters is .
A.	True
B.	False
Answer» B. False

Discussion

12.	When a flip-flop is used in a circuit, we only have to consider the level at and at the active clock edge to know the states of the outputs.
A.	True
B.	False
Answer» C.

Discussion

13.	Cascade means to connect the output of one flip-flop to the clock input of the next.
A.	True
B.	False
Answer» B. False

Discussion

14.	The duty cycle of the most significant bit from a 4-bit (0–9) BCD counter is ________.
A.	10%
B.	20%
C.	50%
D.	80%
Answer» C. 50%

Discussion

15.	List the state of each output pin of a 7447 if RBI = 0, LT = 1, A0 = 1, A1 = 0, A2 = 0, and A3 = 1.
A.	RBO = 0, a = 0, b = 0, c = 0, d = 1, e = 1, f = 0, g = 0
B.	RBO = 1, a = 0, b = 0, c = 0, d = 1, e = 1, f = 0, g = 0
C.	RBO = 0, a = 0, b = 0, c = 0, d = 0, e = 1, f = 0, g = 0
D.	RBO = 1, a = 0, b = 0, c = 0, d = 0, e = 1, f = 0, g = 0
Answer» B. RBO = 1, a = 0, b = 0, c = 0, d = 1, e = 1, f = 0, g = 0

Discussion

16.	The parallel outputs of a counter circuit represent the _____________
A.	Parallel data word
B.	Clock frequency
C.	Counter modulus
D.	Clock count
Answer» E.

Discussion

17.	BCD counter is also known as ____________
A.	Parallel counter
B.	Decade counter
C.	Synchronous counter
D.	VLSI counter
Answer» C. Synchronous counter

Discussion

18.	Three decade counter would have ____________
A.	2 BCD counters
B.	3 BCD counters
C.	4 BCD counters
D.	5 BCD counters
Answer» C. 4 BCD counters

Discussion

19.	Synchronous counter is a type of ____________
A.	SSI counters
B.	LSI counters
C.	MSI counters
D.	VLSI counters
Answer» D. VLSI counters

Discussion

20.	Ripple counters are also called ____________
A.	SSI counters
B.	Asynchronous counters
C.	Synchronous counters
D.	VLSI counters
Answer» C. Synchronous counters

Discussion

21.	A decimal counter has ______ states.
A.	5
B.	10
C.	15
D.	20
Answer» C. 15

Discussion

22.	What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops?
A.	0 to 2n
B.	0 to 2n + 1
C.	0 to 2n – 1
D.	0 to 2n+1/2
Answer» D. 0 to 2n+1/2

Discussion

23.	A counter circuit is usually constructed of ____________
A.	A number of latches connected in cascade form
B.	A number of NAND gates connected in cascade form
C.	A number of flip-flops connected in cascade
D.	A number of NOR gates connected in cascade form
Answer» D. A number of NOR gates connected in cascade form

Discussion

24.	In digital logic, a counter is a device which ____________
A.	Counts the number of outputs
B.	Stores the number of times a particular event or process has occurred
C.	Stores the number of times a clock pulse rises and falls
D.	Counts the number of inputs
Answer» C. Stores the number of times a clock pulse rises and falls

Discussion

25.	What decimal value is required to produce an output at "X" ?
A.	1
B.	1 or 4
C.	2
D.	5
Answer» E.

Discussion

26.	Parallel in/parallel out registers have parallel input and output busses.
A.	1
B.
Answer» B.

Discussion

27.	Basic counters can be cascaded in parallel to increase the number of data bits that the counter can handle.
A.	1
B.
Answer» C.

Discussion

28.	All decade counters are BCD counters.
A.	1
B.
Answer» C.

Discussion

29.	Referring to the function table given below, taking the CLEAR, S1, and S0 inputs all HIGH ________.
A.	will inhibit the operation of the register
B.	will reset the parallel registers and inhibit the serial data inputs
C.	will cause the parallel data inputs to be loaded and passed to the parallel data outputs
D.	will depend on what values are loaded into the parallel data inputs
Answer» D. will depend on what values are loaded into the parallel data inputs

Discussion

30.	In a seven-segment LED display, the BCD must be decoded into a format that can be used to drive the decimal numeric display.
A.	1
B.
Answer» B.

Discussion

31.	A parallel in/serial out shift register enters all data bits simultaneously and transfers them out one bit at a time.
A.	1
B.
Answer» B.

Discussion

32.	A J-K flip-flop excitation table lists the present state, the next state, and the J and K levels required to produce each transition.
A.	1
B.
Answer» B.

Discussion

33.	The duty cycle of the most significant bit from a 4-bit (0‚Äì9) BCD counter is ________.
A.	0.1
B.	0.2
C.	0.5
D.	0.8
Answer» C. 0.5

Discussion

34.	The terminal count of a typical modulus-10 binary counter is 1010.
A.	1
B.
Answer» C.

Discussion

35.	Once an up/down counter begins its count sequence, it cannot be reversed.
A.	1
B.
Answer» C.

Discussion

36.	The ________ counter in the Altera library has controls that allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.
A.	74134
B.	LPM
C.	synchronous
D.	AHDL
Answer» C. synchronous

Discussion

37.	Synchronous binary counters can only be used for the application of timing of digital systems.
A.	1
B.
Answer» C.

Discussion

38.	The decimal equivalent of the largest number that can be stored in a 4-bit binary counter is ________.
A.	8
B.	15
C.	16
D.	32
Answer» C. 16

Discussion

39.	An asynchronous counter differs from a synchronous counter in the method of clocking.
A.	1
B.
Answer» B.

Discussion

40.	Shift register counters use logic functions to reset the registers when the desired count is reached.
A.	1
B.
Answer» C.

Discussion

41.	Most sequential circuits contain a combinational logic section and a memory section.
A.	1
B.
Answer» B.

Discussion

42.	________ is the output frequency of the counter shown below.
A.	4 MHz
B.	20 kHz
C.	210.5 kHz
D.	800 Hz
Answer» C. 210.5 kHz

Discussion

43.	The given circuit represents a(n) ________.
A.	four-bit binary counter
B.	asynchronous BCD decade counter
C.	synchronous BCD decade counter
D.	BCD-to-decimal decoder
Answer» D. BCD-to-decimal decoder

Discussion

44.	When implementing a complete system application using IC counter chips, output devices such as LED indicators must be configured to operate from the counter outputs.
A.	1
B.
Answer» C.

Discussion

45.	Shift registers are used to store and transfer data.
A.	1
B.
Answer» B.

Discussion

46.	Generally speaking, the synchronous counter requires more circuitry than an asynchronous counter.
A.	1
B.
Answer» B.

Discussion

47.	Assume you want to determine the timing diagram for a 4-bit counter using an oscilloscope. The best choice for an oscilloscope trigger signal is ________.
A.	the most significant bit (MSB)
B.	the least significant bit (LSB)
C.	the clock signal
D.	from a composite of the MSB and LSB
Answer» D. from a composite of the MSB and LSB

Discussion

48.	The term synchronous, as applied to counter operations, means that the counter is clocked such that each flip-flop in the counter is triggered at the same time.
A.	1
B.
Answer» B.

Discussion

49.	A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most significant bit is ________.
A.	1.25 kHz
B.	2.50 kHz
C.	160 kHz
D.	320 kHz
Answer» B. 2.50 kHz

Discussion

50.	Asynchronous counters are known as modulus counters.
A.	1
B.
Answer» C.

Discussion

Explore topic-wise MCQs in Digital Electronics.

A MOD-16 ripple counter is holding the count 1001. What will the count be after 31 clock pulses?

After 10 clock cycles, and assuming that the DATA input had returned to 0 following the storage sequence, what values would be stored in 4, 3, 2, 1, 0 of the register in Figure 7-5?

A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (t) is ________.

Any divide-by- counter can be formed by using external gating to ________ at a predetermined number.

The designation means that the ________.

What is the maximum delay that can occur if four flip-flops are connected as a ripple counter and each flip-flop has propagation delays of = 22 ns and = 15 ns?

The term refers to events that do not occur at the same time.

The term , as applied to counter operations, means that the counter is clocked such that each flip-flop in the counter is triggered at the same time.

A J-K flip-flop excitation table lists the present state, the next state, and the and levels required to produce each transition.

A parallel in/serial out shift register enters all data bits simultaneously and transfers them out one bit at a time.

Another term used to describe up/down counters is .

When a flip-flop is used in a circuit, we only have to consider the level at and at the active clock edge to know the states of the outputs.

Cascade means to connect the output of one flip-flop to the clock input of the next.

The duty cycle of the most significant bit from a 4-bit (0–9) BCD counter is ________.

List the state of each output pin of a 7447 if RBI = 0, LT = 1, A0 = 1, A1 = 0, A2 = 0, and A3 = 1.

The parallel outputs of a counter circuit represent the _____________

BCD counter is also known as ____________

Three decade counter would have ____________

Synchronous counter is a type of ____________

Ripple counters are also called ____________

A decimal counter has ______ states.

What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops?

A counter circuit is usually constructed of ____________

In digital logic, a counter is a device which ____________

What decimal value is required to produce an output at "X" ?

Parallel in/parallel out registers have parallel input and output busses.

Basic counters can be cascaded in parallel to increase the number of data bits that the counter can handle.

All decade counters are BCD counters.

Referring to the function table given below, taking the CLEAR, S1, and S0 inputs all HIGH ________.

In a seven-segment LED display, the BCD must be decoded into a format that can be used to drive the decimal numeric display.

A parallel in/serial out shift register enters all data bits simultaneously and transfers them out one bit at a time.

A J-K flip-flop excitation table lists the present state, the next state, and the J and K levels required to produce each transition.

The duty cycle of the most significant bit from a 4-bit (0‚Äì9) BCD counter is ________.

The terminal count of a typical modulus-10 binary counter is 1010.

Once an up/down counter begins its count sequence, it cannot be reversed.

The ________ counter in the Altera library has controls that allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.

Synchronous binary counters can only be used for the application of timing of digital systems.

The decimal equivalent of the largest number that can be stored in a 4-bit binary counter is ________.

An asynchronous counter differs from a synchronous counter in the method of clocking.

Shift register counters use logic functions to reset the registers when the desired count is reached.

Most sequential circuits contain a combinational logic section and a memory section.

________ is the output frequency of the counter shown below.

The given circuit represents a(n) ________.

When implementing a complete system application using IC counter chips, output devices such as LED indicators must be configured to operate from the counter outputs.

Shift registers are used to store and transfer data.

Generally speaking, the synchronous counter requires more circuitry than an asynchronous counter.

Assume you want to determine the timing diagram for a 4-bit counter using an oscilloscope. The best choice for an oscilloscope trigger signal is ________.

The term synchronous, as applied to counter operations, means that the counter is clocked such that each flip-flop in the counter is triggered at the same time.

A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most significant bit is ________.

Asynchronous counters are known as modulus counters.