Explore topic-wise MCQs in Vlsi.

This section includes 18 Mcqs, each offering curated multiple-choice questions to sharpen your Vlsi knowledge and support exam preparation. Choose a topic below to get started.

1.

In CMOS domino logic _______ is possible.

A. inverting structure
B. non inverting structure
C. inverting and non inverting structure
D. very complex design
Answer» C. inverting and non inverting structure
Discussion
2.

CMOS domino logic has

A. smaller parasitic capacitance
B. larger parasitic capacitance
C. low operating speed
D. very large parasitic capacitance
Answer» B. larger parasitic capacitance
Discussion
3.

CMOS domino logic occupies

A. smaller area
B. larger area
C. smaller & larger area
D. none of the mentioned
Answer» B. larger area
Discussion
4.

CMOS domino logic is same as ______ with inverter at the output line.

A. clocked CMOS logic
B. dynamic CMOS logic
C. gate logic
D. switch logic
Answer» C. gate logic
Discussion
5.

In CMOS domino logic _____ is used.

A. two phase clock
B. three phase clock
C. one phase clock
D. four phase clock
Answer» D. four phase clock
Discussion
6.

In dynamic CMOS logic _____ is used.

A. two phase clock
B. three phase clock
C. one phase clock
D. four phase clock
Answer» E.
Discussion
7.

The power dissipation in Pseudo-nMOS is reduced to about ________ compared to nMOS device.

A. 50%
B. 30%
C. 60%
D. 70%
Answer» D. 70%
Discussion
8.

CMOS_DOMINO_LOGIC_HAS?$

A. smaller parasitic capacitance
B. larger parasitic capacitance
C. low operating speed
D. very large parasitic capacitance
Answer» B. larger parasitic capacitance
Discussion
9.

In CMOS domino logic _______ is possible$

A. inverting structure
B. non inverting structure
C. inverting and non inverting structure
D. very complex design
Answer» C. inverting and non inverting structure
Discussion
10.

CMOS domino logic occupie?

A. smaller area
B. larger area
C. both of the mentioned
D. none of the mentioned
Answer» B. larger area
Discussion
11.

CMOS domino logic is same as ______ with inverter at the output line

A. clocked CMOS logic
B. dynamic CMOS logic
C. gate logic
D. switch logic
Answer» C. gate logic
Discussion
12.

In CMOS domino logic _____ is used

A. two phase clock
B. three phase clock
C. one phase clock
D. four phase clock
Answer» D. four phase clock
Discussion
13.

In clocked CMOS logic, rise time and fall time are

A. faster
B. slower
C. faster first and then slows down
D. slower first and then speeds up
Answer» C. faster first and then slows down
Discussion
14.

In clocked CMOS logic, output in evaluated in

A. on period
B. off period
C. both periods
D. half of on period
Answer» B. off period
Discussion
15.

In dynamic CMOS logic _____ is used

A. two phase clock
B. three phase clock
C. one phase clock
D. four phase clock
Answer» E.
Discussion
16.

Pseudo-nMOS has higher pull-up resistance than nMOS device.

A. true
B. false
Answer» B. false
Discussion
17.

The power dissipation in Pseudo-nMOS is reduced to about ____ compared to nMOS device

A. 50%
B. 30%
C. 60%
D. 70%
Answer» D. 70%
Discussion
18.

In Pseudo-nMOS logic, n transistor operates in

A. cut off region
B. saturation region
C. resistive region
D. non saturation region
Answer» C. resistive region
Discussion