Which verification capture‚Äö√Ñ√∂‚àö√ë‚àö¬•s teh design intent and not physical layout?$

transistor level layout language

Which verification capture‚Äö√Ñ√∂‚àö√ë‚àö¬•s

1.	Which verification capture‚Äö√Ñ√∂‚àö√ë‚àö¬•s teh design intent and not physical layout?$
A.	mask level layout language
B.	transistor level layout language
C.	circuit description language
D.	switch level layout language
Answer» D. switch level layout language