Using the schematic diagram of a TTL NAND gate, determine the state of – McqOptions

MCQOPTIONS

1.	Using the schematic diagram of a TTL NAND gate, determine the state of each transistor (ON or OFF) when all inputs are high.
A.	Q1-ON, Q2-OFF, Q3-ON, Q4-OFF
B.	Q1-ON, Q2-ON, Q3-OFF, Q4-OFF
C.	Q1-OFF, Q2-OFF, Q3-ON, Q4-ON
D.	Q1-OFF, Q2-ON, Q3-OFF, Q4-ON
Answer» E.

Discussion

No Comment Found

Related MCQs

Assume that a particular IC has a supply voltage () equal to +5 V and = 10 mA and = 23 mA. What is the power dissipation for the chip?
The problem of the V of a TTL IC being too low to drive a CMOS circuit and meet the CMOS requirement of V is usually easily overcome by:
Why are the maximum value of and the minimum value of used to determine the noise margin rather than the typical values for these parameters?
The rise time () is the time it takes for a pulse to rise from its ________ point up to its ________ point. The fall time () is the length of time it takes to fall from the ________ to the ________ point.
The problem of interfacing IC logic families that have different supply voltages ('s) can be solved by using a:
How is the speed–power product of a logic family determined?
As a general rule, the lower the value of the speed–power product, the better the device because of its:
Interfacing (74HCMOS to 74ALSTTl or 74TTL to 74LSTTL) can be done with no danger.
Schottky logic overcomes the saturation and stored charge problem by placing a Schottky diode across the base-to-collector junction.
PMOS and NMOS are commonly used for small memories and microprocessors.