The output of a flip-flop is normally HIGH when the device is in the – McqOptions

MCQOPTIONS

1.	The output of a flip-flop is normally HIGH when the device is in the "CLEAR" or "RESET" state.
A.	True
B.	False
Answer» C.

Discussion

No Comment Found

Related MCQs

A gated S-R flip-flop goes into the SET condition when is HIGH, is LOW, and is HIGH.
VHDL require a special designation for an output with a feedback.
The term CLEAR always means that .
What does the triangle on the clock input of a flip-flop mean?
The toggle condition in a master-slave flip-flop means that and will switch to their ________ state(s) at the ________.
An RC circuit used in a nonretriggerable 74121 one-shot has an Rof 49 k and a C of 0.2 F. The pulse width (t) is approximately ________.
With four flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?
A 555 operating as a monostable multivibrator has a C = 0.01 F. Determine R for a pulse width of 2 ms.
Why are the and inputs of a gated flip-flop said to be synchronous?
Gated flip-flops are called asynchronous because the output responds immediately to input changes.