In VHDL, local signals are declared in the VARIABLE section, which is placed between the SUBDESIGN section and the logic section.

In VHDL, local signals are declared in the VARIABLE section, which is

1.	In VHDL, local signals are declared in the VARIABLE section, which is placed between the SUBDESIGN section and the logic section.
A.	1
B.
C.	1
D.
Answer» C. 1