In a feedback-bias configuration, the slope of the dc load line is con – McqOptions

MCQOPTIONS

1.	In a feedback-bias configuration, the slope of the dc load line is controlled by ________.
A.	RG
B.	RD
C.	VDG
D.	None of the above
Answer» C. VDG

Discussion

No Comment Found

Related MCQs

In p-channel FETs, the level of VGS is ________ while the level of VDS is ________.
In a universal JFET bias curve, the horizontal axis is ________.
In a universal JFET bias curve, the vertical scale labeled M is used for finding the solution to the ________ configuration.
In a universal JFET bias curve, the vertical scale labeled m is used to find the solution to the ________ configuration.
The level of VDS is typically between ________ % and ________ % of VDD.
In a JFET, the level of ________ is limited to values between 0 V and –VP.
________ must be considered in the total design process.
For R2 smaller than ________ k the voltage VD is equal to VDD = 16 V.
In a feedback-bias configuration, the slope of the dc load line is controlled by ________.
In an enhancement-type MOSFET, the drain current is zero for levels of VGS less than the ________ level.