A 1 to 8 demultiplexer with data input Din, address inputs S0, S1, and S2, (with S0 as the LSB) and Y̅0 to Y̅ 7 as the eight de-multiplexed output, is to be designed using two 2 to 4 decoders (with enable input E and address input A0 and A1) as shown in the figure. Din, S0, S1, and S2 are to be connected to P, Q, R, and S but not necessarily in this order. The respective input connections to P, Q, R, and S terminals should be

A 1 to 8 demultiplexer with data input Din, address inputs S0, S1, an

1.	A 1 to 8 demultiplexer with data input Din, address inputs S0, S1, and S2, (with S0 as the LSB) and Y̅0 to Y̅ 7 as the eight de-multiplexed output, is to be designed using two 2 to 4 decoders (with enable input E and address input A0 and A1) as shown in the figure. Din, S0, S1, and S2 are to be connected to P, Q, R, and S but not necessarily in this order. The respective input connections to P, Q, R, and S terminals should be
A.	S2, Din, S0, and S1
B.	S1, Din, S0, and S2
C.	Din, S0, S1, and S2
D.	Din, S2, S0, and S1
Answer» E.