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This section includes 23 Mcqs, each offering curated multiple-choice questions to sharpen your Vlsi knowledge and support exam preparation. Choose a topic below to get started.
1. |
Gate minimization technique is used to simplify the logic. |
A. | true |
B. | false |
Answer» B. false | |
2. |
Which is the high level representation of VLSI design? |
A. | problem statement |
B. | logic design |
C. | HDL program |
D. | functional design |
Answer» B. logic design | |
3. |
Physical and electrical specification is given in ____________ |
A. | architectural design |
B. | logic design |
C. | system design |
D. | functional design |
Answer» E. | |
4. |
______ is used in logic design of VLSI. |
A. | LIFO |
B. | FIFO |
C. | FILO |
D. | LILO |
Answer» C. FILO | |
5. |
What is the design flow of VLSI system? |
A. | ii-i-iii-iv |
B. | iv-i-iii-ii |
C. | iii-ii-i-iv |
D. | i-ii-iii-ivView Answer |
Answer» B. iv-i-iii-ii | |
6. |
______ architecture is used to design VLSI. |
A. | system on a device |
B. | single open circuit |
C. | system on a chip |
D. | system on a circuit |
Answer» D. system on a circuit | |
7. |
As die size shrinks, the complexity of making the photomasks ____________ |
A. | increases |
B. | decreases |
C. | remains the same |
D. | cannot be determined |
Answer» B. decreases | |
8. |
_________ is used to deal with effect of variation. |
A. | chip level technique |
B. | logic level technique |
C. | switch level technique |
D. | system level technique |
Answer» E. | |
9. |
The difficulty in achieving high doping concentration leads to ____________ |
A. | error in concentration |
B. | error in variation |
C. | error in doping |
D. | distribution error |
Answer» C. error in doping | |
10. |
Medium scale integration has ____________ |
A. | ten logic gates |
B. | fifty logic gates |
C. | hundred logic gates |
D. | thousands logic gates |
Answer» D. thousands logic gates | |
11. |
VLSI technology uses ________ to form integrated circuit. |
A. | transistors |
B. | switches |
C. | diodes |
D. | buffers |
Answer» B. switches | |
12. |
PHYSICAL_AND_ELECTRICAL_SPECIFICATION_IS_GIVEN_IN?$ |
A. | architectural design |
B. | logic design |
C. | system design |
D. | functional design |
Answer» E. | |
13. |
Gate minimization technique is used to simplify the logic.$ |
A. | true |
B. | false |
Answer» B. false | |
14. |
Which is the high level representation of VLSI design$ |
A. | problem statement |
B. | logic design |
C. | HDL program |
D. | functional design |
Answer» B. logic design | |
15. |
Which provides higher integration density? |
A. | switch transistor logic |
B. | transistor buffer logic |
C. | transistor transistor logic |
D. | circuit level logic |
Answer» D. circuit level logic | |
16. |
______ is used in logic design of VLSI |
A. | LIFO |
B. | FIFO |
C. | FILO |
D. | LILO |
Answer» C. FILO | |
17. |
The design flow of VLSI system is |
A. | |
B. | 2-1-3-4 |
C. | 4-1-3-2 |
Answer» B. 2-1-3-4 | |
18. |
______ architecture is used to design VLSI |
A. | system on a device |
B. | single open circuit |
C. | system on a chip |
D. | system on a circuit |
Answer» D. system on a circuit | |
19. |
As die size shrinks, the complexity of making the photomasks |
A. | increases |
B. | decreases |
C. | remains the same |
D. | cannot be determined |
Answer» B. decreases | |
20. |
_________ is used to deal with effect of variation |
A. | chip level technique |
B. | logic level technique |
C. | switch level technique |
D. | system level technique |
Answer» E. | |
21. |
The difficulty in achieving high doping concentration leads to |
A. | error in concentration |
B. | error in variation |
C. | error in doping |
D. | distrubution error |
Answer» C. error in doping | |
22. |
Medium scale integration has |
A. | ten logic gates |
B. | fifty logic gates |
C. | hundred logic gates |
D. | thousands logic gates |
Answer» D. thousands logic gates | |
23. |
VLSI technology uses ________ to form integrated circuit |
A. | transistors |
B. | switches |
C. | diodes |
D. | buffers |
Answer» B. switches | |