MCQOPTIONS
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MCQOPTIONS
This section includes 21 Mcqs, each offering curated multiple-choice questions to sharpen your Vlsi knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
One pass transistor can be driven through output of another. |
| A. | true |
| B. | false |
| Answer» C. | |
| 2. |
Using _____ long wires are possible. |
| A. | silicide |
| B. | metal |
| C. | polysilicon |
| D. | diffusion |
| Answer» B. metal | |
| 3. |
Propogation delay is given by |
| A. | nrcƮ |
| B. | n2rcƮ |
| C. | nr2cƮ |
| D. | n2cƮ |
| Answer» C. nr2cƮ | |
| 4. |
If f assumes the value e then delay is |
| A. | maximized |
| B. | minimized |
| C. | does not change |
| D. | doubled |
| Answer» C. does not change | |
| 5. |
Which is used to increase Ʈ? |
| A. | parasitic capacitance |
| B. | peripheral capacitance |
| C. | area capacitance |
| D. | load capacitance |
| Answer» B. peripheral capacitance | |
| 6. |
What is the delay value Ʈ for 1.2 micron technology? |
| A. | 0.1 nsec |
| B. | 0.12 nsec |
| C. | 0.046 nsec |
| D. | 0.064 nsec |
| Answer» D. 0.064 nsec | |
| 7. |
1 square Cg is ___________ of MOS transistor. |
| A. | gate to source capacitance |
| B. | gate to drain capacitance |
| C. | source to drain capacitance |
| D. | gate to channel capacitance |
| Answer» E. | |
| 8. |
PROPOGATION_DELAY_IS_GIVEN_BY?$ |
| A. | nrcƮ |
| B. | n<sup>2</sup>rcƮ |
| C. | nr<sup>2</sup>cƮ |
| D. | n<sup>2</sup>cƮ |
| Answer» C. nr<sup>2</sup>c‚Äö√†√ú‚àö√ú | |
| 9. |
One pass transistor can be driven through output of another.$ |
| A. | true |
| B. | false |
| Answer» C. | |
| 10. |
Using _____ long wires are possible$ |
| A. | silicide |
| B. | metal |
| C. | polysilicon |
| D. | diffusion |
| Answer» B. metal | |
| 11. |
Maximum allowable current density in aluminium is |
| A. | 0.1 mA/µm2 |
| B. | 0.5 mA/µm2 |
| C. | 2 mA/µm2 |
| D. | 1 mA/µm2 |
| Answer» E. | |
| 12. |
Pass transistors are allowed to be constructed under |
| A. | diffusion layer |
| B. | polysilicon layer |
| C. | metal layer |
| D. | silicon layer |
| Answer» D. silicon layer | |
| 13. |
If f assumes the value e then delay i? |
| A. | maximized |
| B. | minimized |
| C. | does not change |
| D. | doubled |
| Answer» C. does not change | |
| 14. |
The number of stages N is given by |
| A. | ln(y)/ln(f) |
| B. | ln(f)/ln(y) |
| C. | ln(2y)/ln(f) |
| D. | ln(y)/ln(2f) |
| Answer» B. ln(f)/ln(y) | |
| 15. |
The inverter pair delay is given by |
| A. | (Zp.u./Zp.d.)Ʈ |
| B. | (1+ Zp.u./Zp.d.)Ʈ |
| C. | (1+ Zp.u./Zp.d.)Ʈ |
| D. | (1+ Ʈ)Zp.u./Zp.d. |
| Answer» C. (1+ Zp.u./Zp.d.)‚Äö√†√ú‚àö√ú | |
| 16. |
Which is used to increase Ʈ?$ |
| A. | parasitic capacitance |
| B. | peripheral capacitance |
| C. | area capacitance |
| D. | load capacitance |
| Answer» B. peripheral capacitance | |
| 17. |
What is the delay value Ʈ for 1.2 micron technology?$ |
| A. | 0.1 nsec |
| B. | 0.12 nsec |
| C. | 0.046 nsec |
| D. | 0.064 nsec |
| Answer» D. 0.064 nsec | |
| 18. |
1 square Cg is ______ of MOS transistor |
| A. | gate to source capacitance |
| B. | gate to drain capacitance |
| C. | source to drain capacitance |
| D. | gate to channel capacitance |
| Answer» E. | |
| 19. |
What is the value for peripheral capacitance for 5 micron technology? |
| A. | 4 x 10<sup>(-4)</sup> pf/µm2 |
| B. | 5 x 10<sup>(-4)</sup> pf/µm2 |
| C. | 8 x 10<sup>(-4)</sup> pf/µm2 |
| D. | 12 x 10<sup>(-4)</sup> pf/µm2 |
| Answer» D. 12 x 10<sup>(-4)</sup> pf/¬¨¬®¬¨¬µm2 | |
| 20. |
The impedance ratio for pseudo-nMOS is |
| A. | 4:1 |
| B. | 3:1 |
| C. | 1:4 |
| D. | 1:3 |
| Answer» C. 1:4 | |
| 21. |
The Zp.u./Zp.d. ratio for nMOS inverter is |
| A. | 4:1 |
| B. | 3:1 |
| C. | 1:4 |
| D. | 1:3 |
| Answer» B. 3:1 | |