Explore topic-wise MCQs in Electronics & Communication Engineering.

This section includes 883 Mcqs, each offering curated multiple-choice questions to sharpen your Electronics & Communication Engineering knowledge and support exam preparation. Choose a topic below to get started.

51.

A bus connected between the CPU and the main memory that permits transfer of information between main memory and the CPU is known as

A. DMA bus
B. Memory bus
C. Address bus
D. Control bus
Answer» C. Address bus
Discussion
52.

In 8051, by default:

A. only timer/counter0 interrupt is disabled
B. all interrupts are disabled
C. only System RESET interrupt is disabled
D. only timer/counter1 interrupt is disabled
Answer» C. only System RESET interrupt is disabled
Discussion
53.

In a 8085 microprocessor system with memory mapped I/O

A. I/O devices have 8 bit address
B. I/O devices are accessed using IN and OUT instructions.
C. There can be maximum 256 input and 256 output devices
D. Arithmetic and logic operations can be directly performed with I/O data
Answer» E.
Discussion
54.

Insertion of a record in a circularly linked list involves the modification of:

A. 4 pointers
B. 3 pointers
C. 2 pointers
D. 1 pointers
Answer» D. 1 pointers
Discussion
55.

Accumulator has data FFH. Determine the state of CY, Z and sign flag when:1) 01H is added2) the content of the accumulator is incremented

A. CY = 0, S = 0, Z = 12) CY = 1, S = 1, Z = 0
B. CY = 1, S = 0, Z = 12) CY = same as previous state, S = 0, Z = 1
C. CY = 0, S = 0, Z = 02) CY = same as previous state, S = 1, Z = 1
D. CY = 1, S = 0, Z = 02) CY = 1, S = 0, Z = 0
Answer» C. CY = 0, S = 0, Z = 02) CY = same as previous state, S = 1, Z = 1
Discussion
56.

FAR CALL or FAR JUMP is to branch if program area is outside ________ segment in 8086

A. 4k Byte
B. 16k Byte
C. 32k Byte
D. 64k Byte
Answer» E.
Discussion
57.

In 8085 microprocessor instruction XCHG is:

A. 3-byte instruction
B. 2-byte instruction
C. 5-byte instruction
D. 1-byte instruction
Answer» E.
Discussion
58.

DMA channel facilitates data to move into and out of the system _________

A. on first come first serve basis
B. without program intervention
C. without subroutine
D. with equal time delay
Answer» C. without subroutine
Discussion
59.

Cycle-stealing mode of DMA operation involves:

A. DMA controller takes over the address, data and control buses while a block of data is transferred between memory and an I/O device
B. While the μP is executing a program an interface circuit takes over control of the address, data and control buses when not in use by the μP
C. Data transfer takes place between the I/O device and memory during every alternate clock cycle
D. The DMA controller waits for the μP to finish execution of the program and then takes over the buses.
Answer» D. The DMA controller waits for the μP to finish execution of the program and then takes over the buses.
Discussion
60.

__________ is a primitive that can execute code. It contains an instruction pointer (=program counter) and sometimes has its own stack

A. Process
B. Task
C. Kernel
D. Thread
Answer» E.
Discussion
61.

Consider the following loop MOV CX, 8000hL1 : DEC CX JNZ L1The processor is running at \(\frac{14.7456}{3}\) MHz and DEC CX requires 2 clock cycles and JNZ requires 16 clock cycles. The total time taken is nearly

A. 0.01 s
B. 0.12 s
C. 3.66 s
D. 4.19 s
Answer» C. 3.66 s
Discussion
62.

In 8085 microprocessor, the 16-bit registers used are:

A. Stack pointer and accumulator
B. Program counter and accumulator
C. Stack pointer and program counter
D. Accumulator, stack pointer and program counter
Answer» D. Accumulator, stack pointer and program counter
Discussion
63.

In microprocessor’s stack, what does the operation push cx means?

A. Ch = [sp – 1], cl = [sp – 2] and sp = sp - 2
B. Ch = [sp], cl = [sp – 1] and sp = sp - 2
C. Ch = [sp + 1], cl = [sp] and sp = sp + 2
D. ch = [sp], cl [sp + 1] and sp = sp + 2
Answer» B. Ch = [sp], cl = [sp – 1] and sp = sp - 2
Discussion
64.

Assertion (A): The address bus size in 8086 is 20 bit.Reason (R): Registers size of 8086 microprocessor is 16 bit.

A. Both (A) and (R) are true and (R) is the correct explanation of (A)
B. Both (A) and (R) are true, but (R) is not the correct explanation of (A)
C. (A) is true, but (R) is false
D. (A) is false, but (R) is true
Answer» C. (A) is true, but (R) is false
Discussion
65.

In 8085 MPU, the flag flip flops have ________ status indicators.

A. 5
B. 2
C. 4
D. 1
Answer» B. 2
Discussion
66.

PUSH and POP operations are performed by

A. Program counter register
B. General purpose register
C. Stack pointer register
D. Link register
Answer» D. Link register
Discussion
67.

Assertion (A): Architecturally 8086 μP is totally different from its predecessor 8085 μP but functionally it is downward compatible with 8085.Reason (R): The segmented architecture was introduced in 8086 μP to keep compatibility with 8085 μp.

A. Both (A) and (R) are true and (R) is the correct explanation of (A)
B. Both (A) and (R) are true, but (R) is not the correct explanation of (A)
C. (A) is true, but (R) is false
D. (A) is false, but (R) is true
Answer» B. Both (A) and (R) are true, but (R) is not the correct explanation of (A)
Discussion
68.

Calculate the time required to execute the entire instruction cycle if two machine codes, 0011 1110 and 0011 0010, are stored in memory locations 2000H and 2001H, respectively.If the clock frequency is 2 MHz, the first machine code represents opcode to load data byte in the accumulator and the second code represents data to be loaded in the accumulator.

A. 1.5 μs
B. 0.5 μs
C. 3.5 μs
D. 2.5 μs
Answer» D. 2.5 μs
Discussion
69.

Directions: It consists of two statements, one labelled as the ‘Statement (I)’ and the other as ‘Statement (II)’. You are to examine these two statements carefully and select the answer using the codes given below:Statement (I): Program counter is a register that contains the address of the next instruction to be executed.Statement (II): IR (Instruction Register) is not accessible to programmer.

A. Both Statement (I) and Statement (II) are individually true and Statement (II) is the correct explanation of Statement (I)
B. Both Statement (I) and Statement (II) are individually true but Statement (II) is NOT the correct explanation of Statement (I)
C. Statement (I) is true but Statement (II) is false
D. Statement (I) is false but Statement (II) is true
Answer» C. Statement (I) is true but Statement (II) is false
Discussion
70.

A microcontroller can be considered a self-contained system with a processor, ________and peripherals, and can be used as an embedded system.Choose the most appropriate option.

A. Keyboard
B. memory
C. Tester
D. pre-processor
Answer» C. Tester
Discussion
71.

PLC has become popular, because it performs _________ functions.

A. Data transfer
B. Timing and counting
C. Logical
D. Analog
Answer» C. Logical
Discussion
72.

In a computing device ‘MHz’ is mentioned in the specifications. It refers to

A. size of memory
B. speed of computation
C. clock speed
D. none of the above
Answer» D. none of the above
Discussion
73.

Directions: Each of the next six (6) items consist of two statements, one labeled as the ‘Statement (I)’ and the other as ‘Statement (II)’. Examine these two statements carefully and select the answers to these items using the codes given below:Statement (I): The direction flag D in 8086 selects increment or decrement mode for DI and/ or SI registers.Statement (II): If D = 0, the registers are automatically decremented.

A. Both Statement (I) and Statement (II) are individually true and Statement (II) is the correct explanation of Statement (I).
B. Both Statement (I) and Statement (II) are individually true but Statement (II) is not the correct explanation of Statement (I).
C. Statement (I) is true but Statement (II) is false.
D. Statement (I) is false but Statement (II) is true.
Answer» D. Statement (I) is false but Statement (II) is true.
Discussion
74.

In 8085 μP, the READY signal is useful when the CPU communicates with

A. a Programmable Peripheral Interface Chip
B. a DMA controller chip
C. a slow peripheral chip
D. a fast-peripheral chip
Answer» D. a fast-peripheral chip
Discussion
75.

An instruction used to set the carry flag in a computer can be classified as a

A. Data transfer instruction
B. Arithmetic instruction
C. Logical instruction
D. Program control instruction
Answer» D. Program control instruction
Discussion
76.

In an object oriented language like C++, what does a class hold?

A. data
B. functions
C. both data & functions
D. none of the mentioned
Answer» D. none of the mentioned
Discussion
77.

In Register Indirect Addressing mode the offset address of data is ini) BXii) SIiii) DIiv) DXChoose the correct answer from the code given below:Code:

A. (i) and (iv) are correct
B. (i), (ii) and (iii) are correct
C. (ii), (iii) and (iv) are correct
D. (i), (iii) and (iv) are correct
Answer» C. (ii), (iii) and (iv) are correct
Discussion
78.

DPTR is a _____ bit register.

A. 16
B. 4
C. 8
D. 32
Answer» B. 4
Discussion
79.

An RRC instruction in 8085 will affect which flag(s)?

A. CY, S, Z
B. S
C. CY
D. Z
Answer» D. Z
Discussion
80.

A 'DMA' transfer implies:

A. Direct transfer of data between memory and acccumulator
B. Direct transfer of data between memory and I/O device without the use of μP
C. Transfer of data exclusively within μP registers
D. A fast transfer of data between μP and I/O devices
Answer» C. Transfer of data exclusively within μP registers
Discussion
81.

For Opcode fetch operation in 8085 microprocessor

A. \( S_1=0,S_2=1,\overline{RD} =0,\)
B. \( S_1=0,S_2=1,\overline{RD} =1,\)
C. \( S_1=1,S_2=1,\overline{RD} =0,\)
D. \( S_1=1,S_2=1,\overline{RD} =1\)
Answer» D. \( S_1=1,S_2=1,\overline{RD} =1\)
Discussion
82.

In 8085 microprocessors, which signal is used to insert wait?

A. READY
B. ALE
C. HOLD
D. INTR
Answer» B. ALE
Discussion
83.

8259A Programmable Interrupt Controller uses the following initialization commands:1. ICW12. ICW23. ICW34. ICW4If 8259A is to be used in cascaded and fully nested mode, the ICW1 bits D0 and D1 are

A. 0 and 0
B. 1 and 0
C. 0 and 1
D. 1 and 1
Answer» C. 0 and 1
Discussion
84.

Consider the following statements:1. Auxiliary carry flag is used only by the DAA and DAS instructions2. Zero flag is set to 1 if the two operands compared are equal3. All conditional jumps are long-type jumpsWhich of the above statements are correct?

A. 1, 2 and 3
B. 1 and 2 only
C. 1 and 3 only
D. 2 and 3 only
Answer» C. 1 and 3 only
Discussion
85.

On receiving an interrupt from an I/O device, the CPU:

A. Halts for a predetermined time
B. Branches off to the interrupt services routine after completion of the current instruction
C. Branches off to the interrupt service routine immediately
D. Hands over control of address bus and data bus to the interrupting device
Answer» C. Branches off to the interrupt service routine immediately
Discussion
86.

Directions: The following items consist of two statements, one labeled as “Assertion(A)” and the other labeled as “Reason(R)”. You are to examine the two statements carefully and decide if the Assertion(A) and the Reason(R) are individually true and if so whether the reason is a correct explanation of the assertion. Select your answer to these items using the codes given below and mark your answer accordingly.Assertion (A): In 8086 μp, ALE is provided by the processor to latch the address into the 8282/8283 address latch.Reason (R): Whenever the processor sends a valid address on the multiplexed AD0 - AD15 lines, it also makes the ALE high.

A. Both (A) and (R) are true and (R) is the correct explanation of (A).
B. Both (A) and (R) are true, but (R) is not the correct explanation of (A).
C. (A) is true, but (R) is false.
D. (A) is false, but (R) is true.
Answer» B. Both (A) and (R) are true, but (R) is not the correct explanation of (A).
Discussion
87.

Direction flag is used with

A. String instructions
B. Stack instructions
C. Arithmetic instructions
D. Branch instructions
Answer» B. Stack instructions
Discussion
88.

For the 8085 assembly language program given below, the content of the accumulator after the execution of the program is3000 MVI A, 45H3002 MOV B, A3003 STC3004 CMC3005 RAR3006 XRA B3007 HLT

A. 00 H
B. 45 H
C. 67 H
D. E7 H
Answer» D. E7 H
Discussion
89.

In an 8085 system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this?

A. For POP, the data transceivers remain in the same direction as for instruction fetch (memory to processor), whereas for PUSH their direction has to be reversed.
B. Memory write operations are slower than memory read operations in an 8085 based system.
C. The stack pointer needs to be pre-decremented before writing registers in a PUSH, whereas a POP operation uses the address already in the stack pointer.
D. Order of registers has to be interchanged for a PUSH operation, whereas POP uses their natural order.
Answer» D. Order of registers has to be interchanged for a PUSH operation, whereas POP uses their natural order.
Discussion
90.

How is the status of the carry, auxiliary carry and parity flag affected if write instruction?MOV A#9CADD A, #64H

A. CY = 0, AC = 0, P = 0
B. CY = 1, AC = 1, P = 0
C. CY = 0, AC = 1, P = 0
D. CY = 1, AC = 1, P = 1
Answer» C. CY = 0, AC = 1, P = 0
Discussion
91.

RAL is an example of

A. Immediate Addressing mode
B. Implicit Addressing mode
C. Register Indirect Addressing mode
D. Register Addressing mode
Answer» C. Register Indirect Addressing mode
Discussion
92.

Consider the following instructions:1. LOCK2. STD3. HLT4. CLIWhich of the above are machine control instructions?

A. 1 and 4
B. 1 and 3
C. 2 and 3
D. 2 and 4
Answer» C. 2 and 3
Discussion
93.

Assume that the accumulator and the register C of 8085 microprocessor contain respectively F0 H and 0F H initially. What will be the content of accumulator after the execution of instruction ADD C?

A. 00 H
B. FF H
C. EF H
D. FE H
Answer» C. EF H
Discussion
94.

For each instruction of program in memory, the CPU goes through a

A. Decode-fetch-execute sequence
B. Execute-store-decode sequence
C. Fetch-decode-execute sequence
D. Fetch-execute-decode sequence
Answer» D. Fetch-execute-decode sequence
Discussion
95.

If a 24 MHz Oscillator is used in 8051 microcontrollers, the time taken for Timer to make one increment

A. 1 μ sec
B. 2 μ sec
C. 0.5 μ sec
D. 0.24 μ sec
Answer» D. 0.24 μ sec
Discussion
96.

Output of the assembler in machine codes is referred to as

A. Object program
B. Source program
C. Macro instruction
D. Symbolic addressing
Answer» B. Source program
Discussion
97.

An instruction that causes data to be brought from memory into an accumulator register

A. FETCH
B. LOOP
C. LOAD
D. JUMP
Answer» D. JUMP
Discussion
98.

Keyboards are organised in a matrix. The CPU of 8051 accesses both rows and columns through its ports. So, it can accessA) 4 × 4 matrix of keysB) 8 × 8 matrix of keysC) 16 × 16 matrix of keysD) 2 × 2 matrix of keysE) 32 × 32 matrix of keysChoose the most appropriate answer from the options given below:

A. (B) only
B. (A) only
C. (C) only
D. (D) and (E) only
Answer» B. (A) only
Discussion
99.

8085 instructions with the required number of T states are given below. Which pair is correctly matched?

A. STAX : 8T states
B. SPHL : 6T States
C. SIM : 7 T States
D. STA : 12 T states
Answer» C. SIM : 7 T States
Discussion
100.

In an 8085 microprocessor system, the following program starts at location 0100HLXI SP 00FFLXI H 0701MVI A 20HSUB MThe content of the accumulator when the program counter reaches 0107H is

A. 20 H
B. 02 H
C. 00 H
D. FF H
Answer» D. FF H
Discussion