MCQOPTIONS
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MCQOPTIONS
This section includes 883 Mcqs, each offering curated multiple-choice questions to sharpen your Electronics & Communication Engineering knowledge and support exam preparation. Choose a topic below to get started.
| 101. |
How many bits are required to implement a microprocessor having 115 instructions? |
| A. | 5 bits |
| B. | 6 bits |
| C. | 7 bits |
| D. | 8 bits |
| Answer» D. 8 bits | |
| 102. |
During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)? |
| A. | T1 OP code fetch |
| B. | T2 OP code fetch |
| C. | T3 OP code fetch |
| D. | T4 OP code fetch |
| Answer» D. T4 OP code fetch | |
| 103. |
Multiplexing of address and data lines is used in |
| A. | Intel 8086 |
| B. | Z80 |
| C. | 6502 |
| D. | MC68000 |
| Answer» B. Z80 | |
| 104. |
In 8086 microprocessor, if DS = 1100H, BX = 0200 H and SI = 0500H, the address accessed by MOV CH, [BX + SI] is |
| A. | 00300 H |
| B. | 11700 H |
| C. | 0700 H |
| D. | 01800 H |
| Answer» C. 0700 H | |
| 105. |
A device or a peripheral equipment which is not in direct communication with CPU of a computer is called |
| A. | Off line device |
| B. | On line device |
| C. | Active device |
| D. | Slow device |
| Answer» B. On line device | |
| 106. |
NMI input is |
| A. | Edge Triggererd on Negative edge i.e. 1 to 0 transition |
| B. | Edge Triggererd on Positive edge i.e. 0 to 1 transition |
| C. | Level triggered on 1 |
| D. | Level triggered on 0 |
| Answer» C. Level triggered on 1 | |
| 107. |
Match the columns.PinDescriptiona. D0-D71. Reset Inputb. RESET2. Data Linesc. A0,A13. Internal Address |
| A. | a - 2, b - 1, c - 3 |
| B. | a - 1, b - 2, c - 3 |
| C. | a - 2, b - 3, c - 1 |
| D. | a - 1, b - 3, c - 2 |
| Answer» B. a - 1, b - 2, c - 3 | |
| 108. |
In a microprocessor, the register which holds the address of the next instruction to be fetched is: |
| A. | accumulator |
| B. | program counter |
| C. | stack pointer |
| D. | instructor register |
| Answer» C. stack pointer | |
| 109. |
In 8085 microprocessor, after the execution of RST 5 instruction, the program control shifts to |
| A. | 0030 H |
| B. | 0005 H |
| C. | 0028 H |
| D. | 0024 H |
| Answer» D. 0024 H | |
| 110. |
For 8086 microprocessor, the jump distance in bytes for short jump range is |
| A. | Forward 255 and Backward 256 |
| B. | Forward 127 and Backward 128 |
| C. | Forward 31 and Backward 32 |
| D. | Forward 15 and Backward 16 |
| Answer» C. Forward 31 and Backward 32 | |
| 111. |
Consider the following registers:1. Accumulator and flag registers2. B and C3. D and E4. H and LWhich of these 8-bit registers of 8085 microprocessor can be paired together to make a 16-bit register? |
| A. | 1, 3 and 4 |
| B. | 2, 3 and 4 |
| C. | 1, 2 and 3 |
| D. | 1, 2 and 4 |
| Answer» C. 1, 2 and 3 | |
| 112. |
An ADC is interfaced with a microprocessor as shown in the figure. All signals have been indicated with typical notations. Acquisition of one new sample of the analog input signal by the microprocessor involves |
| A. | one READ cycle only |
| B. | one WRITE cycle only |
| C. | one WRITE cycle followed by one READ cycle |
| D. | one READ cycle followed by one WRITE cycle |
| Answer» D. one READ cycle followed by one WRITE cycle | |
| 113. |
In an 8085 microprocessor, the instruction CMP B has been executed while the content of the accumulator is less than that of register B. As a result - |
| A. | Carry flag will be set but Zero flag will be reset |
| B. | Carry flag will be reset but Zero flag will be set |
| C. | Both Carry flag and Zero flag will be reset |
| D. | Both Carry flag and Zero flag will be set |
| Answer» B. Carry flag will be reset but Zero flag will be set | |
| 114. |
It is desired to multiply the number 0AH by 0BH and store the result in the accumulator. The numbers are available in register B and C respectively. A part of the 8085 program for this purpose is given below.MVI, A, 00HLOOP: _______ _______ _______ _______ HLT ENDThe sequence of instruction to complete the program would be |
| A. | JNZ LOOPADD BDCR C |
| B. | ADD BJNZ LOOPDCR C |
| C. | DCR CJNZ LOOPADD B |
| D. | ADD BDCR CJNZ LOOP |
| Answer» E. | |
| 115. |
In 8085A microprocessor, the operation performed by the instruction LHLD 2100H is |
| A. | (H) ← 21H, (L) ← 00H |
| B. | (H) ← (2100H), (L) ← M (2101H) |
| C. | (H) ← M (2101H), (L) ← M (2100H) |
| D. | (H) ← 00H, (L) ← 21H |
| Answer» D. (H) ← 00H, (L) ← 21H | |
| 116. |
Consider the following:i. Compilersii. Designiii. Evaluationiv. Instruction set architectureWhich of these are included in the present definition of computer architecture to design a full computer system? |
| A. | i, ii and iii |
| B. | i, iii and iv |
| C. | ii, iii and iv |
| D. | i, ii, iii and iv |
| Answer» D. i, ii, iii and iv | |
| 117. |
In 8085 microprocessor, which mode of addressing does the instruction CMP M use? |
| A. | Direct addressing |
| B. | Register addressing |
| C. | Indirect addressing |
| D. | Immediate addressing |
| Answer» D. Immediate addressing | |
| 118. |
In 8085 which are 16 bit registers? |
| A. | Stack counter and Accumulator |
| B. | Program counter and Accumulator |
| C. | Stack pointer and Program counter |
| D. | Accumulator, Stack pointer and Program counter |
| Answer» D. Accumulator, Stack pointer and Program counter | |
| 119. |
In PLC, FRD instruction does the following operation |
| A. | Converts Integer value to BCD value |
| B. | Converts HEX value to Binary value |
| C. | Converts BCD value to HEX value |
| D. | Converts BCD value to integer value |
| Answer» E. | |
| 120. |
An IC that tranforms parallel data to serial in the asynchronous format and vice versa |
| A. | UART |
| B. | USART |
| C. | MODEM |
| D. | RS232C |
| Answer» B. USART | |
| 121. |
A software delay subroutine is written as given below:DELAY:MVIH, 255 D MVIL, 255 DLOOP:DCRL JNZLOOP DCRH JNZLOOPHow many times DCR L instruction will be executed? |
| A. | 255 |
| B. | 510 |
| C. | 65025 |
| D. | 65279 |
| Answer» E. | |
| 122. |
If a memory has 10 address lines and the size of each addressable location (block) is 4 bytes, then what is the maximum storage capacity of the memory? |
| A. | 4 kilobyte |
| B. | 2 kilobyte |
| C. | 1 kilobyte |
| D. | 3 kilobyte |
| Answer» B. 2 kilobyte | |
| 123. |
Assuming LSB at 0 position and MSB at position 7, which bit positions are not used (undefined) in flag register of an 8085 microprocessor? |
| A. | 1, 3, 5 |
| B. | 2, 3, 5 |
| C. | 1, 2, 5 |
| D. | 1, 3, 4 |
| Answer» B. 2, 3, 5 | |
| 124. |
Contents of which memory location is transferred to register AL after execution of the following 8086 program?MOV CX, 2050HMOV DS, CXMOV AL, [F025] |
| A. | 0F025 |
| B. | F0250 |
| C. | 2F525 |
| D. | 20500 |
| Answer» D. 20500 | |
| 125. |
Directions: The question consists of two statements, one labeled as ‘Statement (I)’ and the other labelled as ‘Statement (II)’. You are to examine these two statements carefully and select the answers to these items using the codes given below:Statement (I): Registers are used for storage of small data in the microprocessor.Statement (II): All registers are accessible to the user through instructions. |
| A. | Both Statement (I) and Statement (II) are individually true and Statement (II) is the correct explanation of Statement (I). |
| B. | Both Statement (I) and Statement (II) are individually true, but Statement (II) is not the correct explanation of Statement (I). |
| C. | Statement (I) is true, but Statement (II) is false. |
| D. | Statement (I) is false, but Statement (II) is true. |
| Answer» D. Statement (I) is false, but Statement (II) is true. | |
| 126. |
Direct-Memory Access channel (DMA) facilitates data to move in and out of the system |
| A. | On first-come first-serve basis |
| B. | With equal time delay |
| C. | Without a sub-routine |
| D. | Without programme intervention |
| Answer» E. | |
| 127. |
In a microprocessor, op-code fetch cycle is? |
| A. | Last part of instruction cycle |
| B. | First part of instruction cycle |
| C. | Intermediate part of instruction cycle |
| D. | Data reception through bus |
| Answer» C. Intermediate part of instruction cycle | |
| 128. |
A single bus structure is primarily found in: |
| A. | Main frames |
| B. | Mini and micro computers |
| C. | Super computers |
| D. | High performance machines |
| Answer» C. Super computers | |
| 129. |
A microprocessor with a clock frequency of 100 MHz will have a clock period of: |
| A. | 1 ns |
| B. | 10 ns |
| C. | 100 ns |
| D. | 1000 ns |
| Answer» C. 100 ns | |
| 130. |
Choose the correct statements(s) from the following |
| A. | PROM contains a programmable AND array and a fixed OR array. |
| B. | PLA contains a fixed AND array and a programmable OR array. |
| C. | PROM contains a fixed AND array and a programmable OR array. |
| D. | PLA contains a programmable OR array only |
| Answer» D. PLA contains a programmable OR array only | |
| 131. |
In a 8085 microprocessor the first machine cycle of an instruction is |
| A. | An I/O write cycle |
| B. | A Memory Read Cycle |
| C. | A Memory Write Cycle |
| D. | An op-code Fetch Cycle |
| Answer» E. | |
| 132. |
Match List I with List-II and select the correct answer using the code given below the lists: List I List IIA.Immediate addressing1.LDA 30FFB.Implicit addressing2.MOV A, BC.Register addressing3.LXI H, 2050D.Direct addressing4.RRC |
| A. | A – 3, B – 4, C – 2, D - 1 |
| B. | A – 1, B – 4, C – 2, D - 3 |
| C. | A – 3, B – 2, C – 4, D - 1 |
| D. | A – 1, B – 2, C – 4, D - 3 |
| Answer» B. A – 1, B – 4, C – 2, D - 3 | |
| 133. |
An accumulator contains ______ after the execution of the following instructions in an Intel 8085 Microprocessor:MVI A, 7FH; MVI B, AAH; XRA B |
| A. | DFH |
| B. | AFH |
| C. | 00H |
| D. | D5H |
| Answer» E. | |
| 134. |
Direction: Given question consists of two statements, one labeled as the 'Assertion (A)' and the other as 'Reason (R)'. You are to examine these two statements carefully and select the answers to these items using the codes given below.Assertion (A): Processor level design is heavily based on the use of prototype structures.Reason (R): A prototype design is selected and modified to meet the given performance specifications. |
| A. | Both A and R are individually true and R is the correct explanation of A |
| B. | Both A and R are individually true but R is NOT the correct explanation of A |
| C. | A is true but R is false |
| D. | A is false but R is true |
| Answer» B. Both A and R are individually true but R is NOT the correct explanation of A | |
| 135. |
For the 8085 microprocessor, the interfacing circuit to input 8-bit digital data (DI0 – DI7) from an external device is shown in the figure. The instruction for correct data transfer is |
| A. | MVI A, F8H |
| B. | IN F8 H |
| C. | OUT F8H |
| D. | LDA F8 F8H |
| Answer» E. | |
| 136. |
Assertion (A): Negative values of incremental operator in DO loop are allowed in Fortran 77 but not in earlier versions of Fortran.Reason (R): Fortran 77 has better array facilities than earlier versions of Fortran. |
| A. | oth A and R are correct and R is correct explanation of A |
| B. | oth A and R are correct but R is not correct explanation of A |
| C. | is correct R is wrong |
| D. | is wrong R is correct |
| Answer» C. is correct R is wrong | |
| 137. |
Each instruction in assembly language program has the following fields:Lable fieldMnemonic fieldOperand fieldComment fieldThe correct sequence of these fields is? |
| A. | , 2, 3, 4 |
| B. | , 2, 4, 3 |
| C. | , 1, 3, 4 |
| D. | , 1, 4, 3 |
| Answer» B. , 2, 4, 3 | |
| 138. |
Assertion (A): Each memory chip has its own address latch.Reason (R): ALE signal comes out of microprocessor 8085 and goes to memory chip. |
| A. | oth A and R are correct and R is correct explanation of A |
| B. | oth A and R are correct but R is not correct explanation of A |
| C. | is correct R is wrong |
| D. | is wrong R is correct |
| Answer» E. | |
| 139. |
Assertion (A) : In microprocessors, signals can bus and address buses are multiplexed. They can be demultiplexed by using ALE signals.Reason (R): The 8085 microprocessor signals can be classified into various groups, namely address bus, data bus, a control bus, and status signals, externally initiated signals and acknowledgment, power, and frequency, serial I/O signals. |
| A. | Both (A) and (R) are true and (R) is the correct explanation of (A). |
| B. | Both (A) and (R) are true, but (R) is not the correct explanation of (A) |
| C. | (A) is true, but (R) is false. |
| D. | (A) false, but (R) is true |
| Answer» E. | |
| 140. |
Match the two lists and choose the correct answer from the code given below:List IList II S0S1 (a)00(i)Opcode fetch(b)01(ii)Write(c)10(iii)Read(d)11(iv)Halt |
| A. | (a)-(i), (b)-(ii), (c)-(iii), (d)-(iv) |
| B. | (a)-(iv), (b)-(iii), (c)-(ii), (d)-(i) |
| C. | (a)-(iv), (b)-(iii), (c)-(i), (d)-(ii) |
| D. | (a)-(ii), (b)-(i), (c)-(iii), (d)-(iv) |
| Answer» C. (a)-(iv), (b)-(iii), (c)-(i), (d)-(ii) | |
| 141. |
After the following instructions of 8085 microprocessor is executed the registers BC and HL will contain what values?LXI SP, 2099HLXI B, 424FHLXI H, 64A5HPUSH BPUSH HPOP BPOP HRET |
| A. | HL = 4F42H; BC = A564H |
| B. | BC = 4F42H; HL = A564H |
| C. | HL = 424FH; BC = 64A5H |
| D. | BC = 424FH; HL = 64A5H |
| Answer» D. BC = 424FH; HL = 64A5H | |
| 142. |
8085 MPU is |
| A. | 8 bits |
| B. | 16 bits |
| C. | 32 bits |
| D. | 64 bits |
| Answer» B. 16 bits | |
| 143. |
Among which of the following interrupts has the highest priority? |
| A. | RST 7.5 |
| B. | RST 6.5 |
| C. | INTA |
| D. | TRAP |
| Answer» E. | |
| 144. |
In an 8085 microprocessor, the following program is executedAddress location – instruction2000H XRA A2001H MVI B, 04H2003H MVI A, 03H2005H RAR2006H DCR B2007H JNZ 2005200AH HLTAt the end of program, register A contains |
| A. | 60H |
| B. | 30H |
| C. | 06H |
| D. | 03H |
| Answer» B. 30H | |
| 145. |
In a 8085 microprocessor Parity bit is set, if the number of ones is: |
| A. | Even |
| B. | Odd |
| C. | 1 |
| D. | 0 |
| Answer» B. Odd | |
| 146. |
Match List-I with List-II in case of 8086 microprocessor:List-IList-IIa)BIUi)FIFO buffer that can store up to six bytes of instruction codeb)EUii)Responsible for performing all external bus operationsc)IPiii)Responsible for decoding and execution of all instructionsd)Queueiv)Contains the offset or logical address of the next byte to be read from the CSChoose the correct option from those given below: |
| A. | a-iii; b-iv; c-i; d-ii |
| B. | a-iii; b-i; c-iv; d-i |
| C. | a-ii; b-iii; c-i; d-iv |
| D. | a-ii; b-iii; c-iv; d-i |
| Answer» E. | |
| 147. |
In 8085 microprocessor, the address for ‘TRAP’ input is |
| A. | 0024 H |
| B. | 002C H |
| C. | 0034 H |
| D. | 003C H |
| Answer» B. 002C H | |
| 148. |
In an assembly language program END is a/an |
| A. | Machine instruction |
| B. | Pseudo instruction |
| C. | Micro instruction |
| D. | Interrupt |
| Answer» C. Micro instruction | |
| 149. |
In 8085 microprocessor ______ is the highest priority interrupt |
| A. | INTR |
| B. | RST5.5 |
| C. | RST |
| D. | TRAP |
| Answer» E. | |
| 150. |
As compared to 16 bit microprocessor, 8-bit microprocessors are limited in:1. Speed2. Directly addressable memory3. Data handling capability |
| A. | 1 and 2 only |
| B. | 2 and 3 only |
| C. | 1 and 3 only |
| D. | 1, 2 and 3 |
| Answer» E. | |