Explore topic-wise MCQs in Electronics & Communication Engineering.

This section includes 883 Mcqs, each offering curated multiple-choice questions to sharpen your Electronics & Communication Engineering knowledge and support exam preparation. Choose a topic below to get started.

1.

Read the following statements: A μP generally interfaced to several memory chips and I/O devicesAddress space provided by μP is partitioned into sub sets of addressesAddress map and address partition refer to different terms in address space Which of the above are correct?

A. All
B. 1 and 2 only
C. 2 and 3 only
D. 1, 3 only
Answer» C. 2 and 3 only
Discussion
2.

Consider the following statements An assembler is a program having assembly language program as input and machine language program as output.A macro assembler is an assembler with additional macro facilities.A cross assembler for a μP X is an assembler which executes on source microcomputer with a different CPU than X bit generates code for X.Assemblers generally do not provide macro facilities. Of the above statement

A. All are correct
B. only 1, 2, 3 are correct
C. only 1, 2, 4 are correct
D. only 1, 3, 4 are correct
Answer» C. only 1, 2, 4 are correct
Discussion
3.

Consider the statement 20 X = A + B/C + D * Y Which of the following formulae does the above statement represent?

A. [A].
B. [B].
C. [C].
D. None of the above
Answer» C. [C].
Discussion
4.

For the expression cos (ωt + 0) the correct Pascal equivalent is

A. BETA * JCOS (OMEGA * T + THETA) / SQRT (SQR (BETA) + SQR (OMEGA))
B. BETA COS (OMEGA * T + THETA) / SQRT [SQR (BETA) + SQR (OMEGA)]
C. BETA COS (OMEGA T + THETA) / SQRT [SQR (BETA) + SQR (OMEGA)]
D. None of the above
Answer» B. BETA COS (OMEGA * T + THETA) / SQRT [SQR (BETA) + SQR (OMEGA)]
Discussion
5.

Read the following statements about time and space requirements of microprocessors Space requirement is also known as memory requirement.Space requirement is expressed in terms of bytes.Time requirement is expressed in terms of states.Time requirement is expressed in terms of μ- s. Which of the above statements are correct?

A. 1, 2 and 3 only
B. 1, 2 and 4 only
C. 2 and 3 only
D. 1 and 4 only
Answer» B. 1, 2 and 4 only
Discussion
6.

In an 8085 μP system, the RST instruction will cause an interrupt

A. only if an interrupt service routine is not being executed
B. only if a bit in the interrupt mask is made 0
C. only if interrupts have been enabled by an EI instruction
D. None of these
Answer» D. None of these
Discussion
7.

In 8085 which of the following has highest priority?

A. INTR
B. RST 7.5
C. RST 6.5
D. RST 5.5
Answer» C. RST 6.5
Discussion
8.

Microprocessor 8085 is an enhanced version of ________ with essentially the same instruction set.

A. 6800
B. 8080
C. 8086
D. 8000
Answer» C. 8086
Discussion
9.

Assertion A: 8086 microprocessor is a true 16-bit microprocessor.Reason R: It consists of two main sections, bus interface unit (BIU) and execution unit (EU).Choose the correct answer:

A. Both A) and R) are true and R) is the correct explanation of A)
B. Both A) and R) are true, but R) is not the correct explanation of A)
C. is true, but R) is false
D. is false, but R) is true
Answer» C. is true, but R) is false
Discussion
10.

If operating frequency of an 8086 microprocessor is 10 MHz and, if for the given instruction, the machine cycle consists of 4 T-states, what will be the time taken by the machine cycle to complete the execution of that same instruction when three wait state are inserted?

A. 0.4 μs
B. 0.7μs
C. 7 μs
D. 70 μs
Answer» C. 7 μs
Discussion
11.

A stack is normally used in digital computers to store the return address at the time of a call because

A. Stacks are non-volatile tile memories
B. Stacks have large capacity
C. Information in a stack cannot be altered by other instructions
D. Stacks permit easy nesting of subroutine
Answer» E.
Discussion
12.

In an 8085 microprocessor, which one of the following instructions changes the content of the accumulator?

A. MOV B, M
B. PCHL
C. RNZ
D. SBI BEH
Answer» E.
Discussion
13.

A program that can be used repeatedly throughout a major program is called

A. subroutine
B. loop
C. program module
D. template
Answer» B. loop
Discussion
14.

In minimum mode 8086 microprocessor(i) all control signals are given by the microprocessor chip itself(ii) the remaining components in the system are latches, trans receivers clock generators, memory, and I/O devices(iii) it has more than one microprocessor(iv) facilities are provided for implementing allocation of global resourcesChoose the correct answer from the code given below:Code:

A. (i) and (iii) are correct
B. (i), (iii) and (iv) are correct
C. (i) and (ii) are correct
D. (i) and (iv) are correct
Answer» D. (i) and (iv) are correct
Discussion
15.

A ROM is interfaced to an 8085 CPU as indicated in figure. The address range occupied by the ROM is

A. 0000 - 0FFF
B. 0000 - 1FFF
C. 0000 - 2FFF
D. 8000 - 9FFF
Answer» C. 0000 - 2FFF
Discussion
16.

For an 8085 microprocessor, the value of (the number of maskable interrupts) – (the number of non-maskable interrupts) is:

A. 4
B. 3
C. 2
D. 1
Answer» C. 2
Discussion
17.

Intel 8085 is an _____ MUP

A. 8-bit NMOS
B. 8-bit CMOS
C. 8-bit PMOS
D. 8-bit HMOS
Answer» B. 8-bit CMOS
Discussion
18.

Booths algorithm is used for

A. floating point division
B. restoring division
C. integer multiplication
D. square root
Answer» D. square root
Discussion
19.

In 8085 microprocessor, initially the number decimal 8 is stored. If instruction RAL is executed twice on this number, the final number stored will be

A. decimal 8
B. decimal 800
C. decimal 32
D. decimal 2
Answer» D. decimal 2
Discussion
20.

If a program with 5 instructions is executed in 7 clock cycles, then CPI is ______.

A. 1.4
B. 1.5
C. 1
D. 2
Answer» B. 1.5
Discussion
21.

In the instruction MOV A, M

A. the content of memory addressed by HL pair is moved to A register
B. The content of A register is moved to memory location addressed by HL pair
C. the 8 bit data is moved to A register 8 bit
D. none of these
Answer» B. The content of A register is moved to memory location addressed by HL pair
Discussion
22.

In 8085 microprocessor with memory-mapped I/O which of the following is true?

A. I/O devices have 16 bit addresses
B. I/O devices are accessed during IN and OUT instructions
C. There can be a maximum of 256 input and 256 output devices
D. Logic operations cannot be performed
Answer» B. I/O devices are accessed during IN and OUT instructions
Discussion
23.

Consider the following instruction:ElMVI A, 08H SIM It means

A. disable all interrupts
B. enable all interrupts
C. disable RST 7.5 and 6.5
D. enable RST 7.5 and 6.5
Answer» C. disable RST 7.5 and 6.5
Discussion
24.

In order to generate continuous square wave using 8254 timer, it must be programmed in

A. mode 0
B. mode 1
C. mode 2
D. mode 3
Answer» E.
Discussion
25.

In 8086, the physical address of an instruction contains _______ bits.

A. 10
B. 16
C. 18
D. 20
Answer» E.
Discussion
26.

I/O mapped system identify their input/output devices by giving them an:

A. 8 bit port number
B. 16 bit port number
C. 8 bit buffer number
D. 16 bit buffer number
Answer» B. 16 bit port number
Discussion
27.

In 8085 microprocessors how many hardware interrupts are maskable?

A. 2
B. 3
C. 4
D. 5
Answer» D. 5
Discussion
28.

In microprocessor WAIT instruction is used for:

A. make processor wait during DMA operation
B. make processor wait during power interrupt processing
C. make processor wait during power shut down
D. interface slow peripherals to processor
Answer» E.
Discussion
29.

For which of the following instructions, 9-bits are involved in the rotation?

A. RR A
B. RL A
C. RRC A
D. SWAP A
Answer» D. SWAP A
Discussion
30.

How many machine cycles are required by STA instruction?

A. 2
B. 3
C. 4
D. 5
Answer» D. 5
Discussion
31.

If the memory chip size is 1024 × 4, the number of memory chips required to design 8 k memory is

A. 8
B. 256
C. 16
D. 32
Answer» D. 32
Discussion
32.

Directions: It consists of two statements, one labelled as the ‘Statement (I)’ and the other as ‘Statement (II). Examine these two statements carefully and select the answer using the codes given below:Statement (I): Branch instructions in a microprocessor are used to change the sequence of program.Statement (II): All logical instructions are branch instructions.

A. Both Statement (I) and Statement (II) are individually true and Statement (II) is the correct explanation of Statement (I)
B. Both Statement (I) and Statement (II) are individually true but Statement (II) is not the correct explanation of Statement (I)
C. Statement (I) is true but Statement (II) is false
D. Statement (I) is false but Statement (II) is true
Answer» D. Statement (I) is false but Statement (II) is true
Discussion
33.

In 8085 microprocessor system, the direct addressing instruction is

A. MOV A, B
B. MVI B, 0A H
C. MOV C, M
D. STA address
Answer» E.
Discussion
34.

In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectively

A. B and F
B. A and F
C. H and F
D. A and C
Answer» C. H and F
Discussion
35.

In an 8085 microprocessor, after the execution of XRA A instruction

A. the carry flag is set
B. the accumulator contains FFH
C. the zero flag is set
D. the accumulator contents are shifted left by one bit
Answer» D. the accumulator contents are shifted left by one bit
Discussion
36.

In the following 8085 assembly language program, assume that the carry flag is initially reset. What is the content of the accumulator after the execution of the program?MVI A, O4HRRCMOV B, ARLCRLCADD BRRC

A. O2H
B. OSH
C. 15H
D. 25H
Answer» C. 15H
Discussion
37.

A USTART chip provides ______

A. half duplex operation
B. full duplex operation
C. duplex operation
D. full duplex operation but cannot work in asynchronous mode
Answer» E.
Discussion
38.

"Cycle Stealing" in microprocessor parlance refers to

A. Special type of DMA access by an external device
B. RESET operation at power ON by microprocessor
C. Interrupt Acknowledge cycle
D. none of above
Answer» B. RESET operation at power ON by microprocessor
Discussion
39.

In VHDL all the statements written inside a process statement are _________

A. Concurrent
B. Sequential
C. Both (1) and (2)
D. None of the above
Answer» D. None of the above
Discussion
40.

An Intel 8085 processor is executing the program given below:MVI A, 10HMVI B, 10HBACK: NOPADD BRLCJNC BACKHLTThe number of times that the operation NOP will be executed is

A. 1
B. 2
C. 3
D. 4
Answer» D. 4
Discussion
41.

Match the two lists and choose the correct answer from the code given below:List IList II(a) LDA addr(i) Arithmetic group(b) ACI data(ii) Data transfer group(c) ORI data(iii) Logical group(d) JZ addr(iv) Branch control group

A. (a)-(ii), (b)-(i), (c)-(iii), (d)-(iv)
B. (a)-(i), (b)-(ii), (c)-(iii), (d)-(iv)
C. (a)-(iii), (b)-(ii), (c)-(i), (d)-(iv)
D. (a)-(iv), (b)-(iii), (c)-(ii), (d)-(i)
Answer» B. (a)-(i), (b)-(ii), (c)-(iii), (d)-(iv)
Discussion
42.

A processor ha s32-bit architecture. Each instruction is 1 word long (32 bits). It has 64 registers. It supports 50 instructions, which have 2 register operands + 1 immediate operand. Assuming that the immediate operand is an unsigned integer, what is its maximum value?

A. 16383
B. 32767
C. 65536
D. 1024
Answer» B. 32767
Discussion
43.

A small code of 8085 as given below, is executedMVI A, 7FHORA ACPI A2HThe contents of the accumulator and flags after execution are

A. A = DD, S = 1, Z = 0, CY = 0
B. A = 7F, S = 1, Z = 0, CY = 1
C. A = DD, S = 0, Z = 1, CY = 0
D. A = 7F, S = 0, Z = 1, CY = 1
Answer» C. A = DD, S = 0, Z = 1, CY = 0
Discussion
44.

Match the following list:List – I (8085 Instruction)List – II (Addressing mode)a) LXI H, 3400 Hi) Directb) STA 3600 Hii) Register Indirectc) STA X Biii) Immediated) ADD Biv) Register Correct code are:

A. (a) – (iv), (b) – (ii), (c) – (i), (d) – (iii)
B. (a) – (i), (b) – (iii), (c) – (iv), (d) – (ii)
C. (a) – (iii), (b) – (i), (c) – (ii), (d) – (iv)
D. (a) – (iii), (b) – (iv), (c) – (ii), (d) – (i)
Answer» D. (a) – (iii), (b) – (iv), (c) – (ii), (d) – (i)
Discussion
45.

A 16-bit microprocessor has twenty address lines (A0 to A19) and 16 data lines. The higher eight significant lines of the data bus of the processor are tied to the 8-data lines of a 16 Kbyte memory that can store one byte in each of its 16K address locations. The memory chip should map onto contiguous memory locations and occupy only 16 Kbyte of memory space. Which of the following statement(s) is/are correct with respect to the above design?

A. If the 16 Kbyte of memory chip is mapped with a starting address of 80000H, then the ending address will be 83FFFH.
B. The active high chip-select needed to map the 16 Kbyte memory with a starting address at F0000H is given by the logic expression (A19 · A18 · A17 · A16).
C. The 16 Kbyte memory cannot be mapped with contiguous address locations with a starting address as 0F000H using only A19 to A14 for generating chip select.
D. The above chip cannot be interfaced as the width of the data bus of the processor and the memory chip differs.
Answer» B. The active high chip-select needed to map the 16 Kbyte memory with a starting address at F0000H is given by the logic expression (A19 · A18 · A17 · A16).
Discussion
46.

Consider the following 8085 interrupts:1. TRAP2. INTR3. RST 64. RST 7.55. RST 0The software interrupts are:

A. 1 and 3 only
B. 2 and 6 only
C. 3 and 5 only
D. 1, 2, 3, 4 and 5
Answer» D. 1, 2, 3, 4 and 5
Discussion
47.

A microprocessor based safety control system installed in a nuclear power plant must be stress tested under which of the following conditions?1. Ageing due to radiation2. Thermal stresses3. Seismic vibration4. Inadequate nuclear reactor coolant

A. 1 and 2 only
B. 2 and 4 only
C. 1, 2 and 3 only
D. 1, 2, 3 and 4
Answer» D. 1, 2, 3 and 4
Discussion
48.

A memory with 8-bit data bus and 8-bit address bus can store a maximum of

A. 256 bytes
B. 256 bits
C. 1K bytes
D. 512 bytes
Answer» B. 256 bits
Discussion
49.

In 8051, for serial data communication, what does mode 1 means?

A. Multiprocessor variable mode
B. Standard UART mode
C. Multiprocessor fixed mode
D. Shift register mode
Answer» C. Multiprocessor fixed mode
Discussion
50.

According to Flynn’s classification, which architecture is of only theoretical interest and no practical system has been developed based on it?

A. Single Instruction Single Data (SISD)
B. Single Instruction Multiple Data (SIMD)
C. Multiple Instruction Single Data (MISD)
D. Multiple Instruction Multiple Data (MIMD)
Answer» D. Multiple Instruction Multiple Data (MIMD)
Discussion