MCQOPTIONS
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MCQOPTIONS
This section includes 24 Mcqs, each offering curated multiple-choice questions to sharpen your Vlsi knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
BJT gain should be ______ to avoid latch-up effect. |
| A. | increased |
| B. | decreased |
| C. | should be maintained constant |
| D. | changed randomly |
| Answer» C. should be maintained constant | |
| 2. |
Latch-up is brought about by BJTs __________ |
| A. | with positive feedback |
| B. | with negative feedback |
| C. | with no feedback |
| D. | without BJT |
| Answer» B. with negative feedback | |
| 3. |
Latch-up is the generation of __________ |
| A. | low impedance path |
| B. | high impedance path |
| C. | low resistance path |
| D. | high resistance path |
| Answer» B. high impedance path | |
| 4. |
To reduce latch-up effect substrate resistance should be high. |
| A. | true |
| B. | false |
| Answer» C. | |
| 5. |
The reduction in carrier lifetime brings about __________ |
| A. | reduction in alpha |
| B. | reduction in beta |
| C. | reduction in current |
| D. | reduction in voltage |
| Answer» C. reduction in current | |
| 6. |
The parasitic PNP transistor has the effect of _______ carrier lifetime. |
| A. | increasing |
| B. | decreasing |
| C. | exponentially decreasing |
| D. | exponentially increasing |
| Answer» C. exponentially decreasing | |
| 7. |
Which one of the following is the main factor for reducing the latch-up effect? |
| A. | reduced p-well resistance |
| B. | reduced n-well resistance |
| C. | increased n-well resistance |
| D. | increased p-well resistance |
| Answer» C. increased n-well resistance | |
| 8. |
Which process produces a circuit which is less prone to latch-up effect? |
| A. | CMOS |
| B. | nMOS |
| C. | pMOS |
| D. | BiCMOS |
| Answer» E. | |
| 9. |
Latch-up can be induced by __________ |
| A. | incident radiation |
| B. | reflected radiation |
| C. | etching |
| D. | diffracted radiation |
| Answer» B. reflected radiation | |
| 10. |
In latch-up condition, parasitic component gives rise to __________ conducting path. |
| A. | low resistance |
| B. | high resistance |
| C. | low capacitance |
| D. | high capacitance |
| Answer» B. high resistance | |
| 11. |
TO_REDUCE_LATCH-UP_EFFECT_SUBSTRATE_RESISTANCE_SHOULD_BE_HIGH.?$ |
| A. | true |
| B. | false |
| Answer» C. | |
| 12. |
Latch-up is brought about by BJTs$ |
| A. | with positive feedback |
| B. | with negative feedback |
| C. | with no feedback |
| D. | without BJT |
| Answer» B. with negative feedback | |
| 13. |
Latch-up is the generation of$ |
| A. | low impedance path |
| B. | high impedance path |
| C. | low resistance path |
| D. | high resistance path |
| Answer» B. high impedance path | |
| 14. |
BJT gain should be ______ to avoid latch-up effect |
| A. | increased |
| B. | decreased |
| C. | should be maintained constant |
| D. | changed randomly |
| Answer» C. should be maintained constant | |
| 15. |
Sudden transient in power can cause latch-up. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 16. |
The reduction in carrier lifetime brings abou? |
| A. | reduction in alpha |
| B. | reduction in beta |
| C. | reduction in current |
| D. | reduction in voltage |
| Answer» C. reduction in current | |
| 17. |
The parasitic pnp transistor has the effect of _______ carrier lifetime |
| A. | increasing |
| B. | decreasing |
| C. | exponentially decreasing |
| D. | exponentially increasing |
| Answer» C. exponentially decreasing | |
| 18. |
One of the factor in reducing the latch-up effect is |
| A. | reduced p-well resistance |
| B. | reduced n-well resistance |
| C. | increased n-well resistance |
| D. | increased p-well resistance |
| Answer» C. increased n-well resistance | |
| 19. |
Which process produces circuit which are less prone to latch-up effect? |
| A. | CMOS |
| B. | nMOS |
| C. | pMOS |
| D. | BiCMOS |
| Answer» E. | |
| 20. |
What can be introduced to reduce the latch-up effect? |
| A. | latch-up rings |
| B. | guard rings |
| C. | latch guard rings |
| D. | substrate rings |
| Answer» C. latch guard rings | |
| 21. |
Substrate doping level should be decreased to avoid the latch-up effect. |
| A. | true |
| B. | false |
| Answer» C. | |
| 22. |
How many transistors might bring up latch up effect in p-well structure? |
| A. | two |
| B. | three |
| C. | one |
| D. | four |
| Answer» B. three | |
| 23. |
Latch-up can be induced by |
| A. | incident radiation |
| B. | reflected radiation |
| C. | etching |
| D. | diffracted radiation |
| Answer» B. reflected radiation | |
| 24. |
In latch-up condition, parasitic component gives rise to __________ conducting path |
| A. | low resistance |
| B. | high resistance |
| C. | low capacitance |
| D. | high capacitance |
| Answer» B. high resistance | |