MCQOPTIONS
Saved Bookmarks
This section includes 19 Mcqs, each offering curated multiple-choice questions to sharpen your Vlsi knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
In direct coupled logic, the input transistor base is connected to |
| A. | base output |
| B. | emitter output |
| C. | collector output |
| D. | ground |
| Answer» D. ground | |
| 2. |
The ratio of Zp.u./Zp.d. for E-MESFET is |
| A. | 1/10 |
| B. | 10/1 |
| C. | 4/1 |
| D. | 1/4 |
| Answer» C. 4/1 | |
| 3. |
To improve packing density, gate length should be smaller. |
| A. | true |
| B. | false |
| Answer» C. | |
| 4. |
For E-MESFET, Vinv is set in midway between |
| A. | Vdd and Vss |
| B. | Vt and Vin |
| C. | Vt and Vout |
| D. | barrier potential and ground |
| Answer» E. | |
| 5. |
For equal margin, Vinv is set as ______ of logic voltage swing. |
| A. | equal |
| B. | half of |
| C. | one third |
| D. | twice |
| Answer» C. one third | |
| 6. |
TO_IMPROVE_PACKING_DENSITY,_GATE_LENGTH_SHOULD_BE_SMALLER.?$ |
| A. | true |
| B. | false |
| Answer» C. | |
| 7. |
In direct coupled logic, the input transistor base is connected to$ |
| A. | base output |
| B. | emitter output |
| C. | collector output |
| D. | ground |
| Answer» D. ground | |
| 8. |
The ratio of Zp.u./Zp.d. for E-MESFET is$ |
| A. | 1/10 |
| B. | 10/1 |
| C. | 4/1 |
| D. | 1/4 |
| Answer» C. 4/1 | |
| 9. |
For cascade inverters, the relation suitable is |
| A. | Vin = Vout > Vinv |
| B. | Vin = Vout = Vinv |
| C. | Vin < Vout > Vinv |
| D. | Vin > Vout = Vinv |
| Answer» C. Vin < Vout > Vinv | |
| 10. |
Direct-coupled logic is easy to design. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 11. |
For E-MESFET, Vinv is set in midway betwee? |
| A. | Vdd and Vss |
| B. | Vt and Vin |
| C. | Vt and Vout |
| D. | barrier potential and ground |
| Answer» E. | |
| 12. |
For equal margin, Vinv is set as ______ of logic voltage swing |
| A. | equal |
| B. | half of |
| C. | one third |
| D. | twice |
| Answer» C. one third | |
| 13. |
Inverter threshold voltage is the point where |
| A. | Vin = Vt |
| B. | Vout = Vt |
| C. | Vin = Vout |
| D. | Vout lesser than Vin |
| Answer» D. Vout lesser than Vin | |
| 14. |
When current begins to flow, output voltage |
| A. | increases |
| B. | decreses |
| C. | remains constant |
| D. | does not get affected |
| Answer» C. remains constant | |
| 15. |
Maximum voltage across enhancement mode device corresponds to minimum voltage across depletion mode device. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 16. |
In DCFL inverter, enhancement mode device is called as |
| A. | pull down transistor |
| B. | pull up transistor |
| C. | buffer |
| D. | combiner |
| Answer» B. pull up transistor | |
| 17. |
For depletion mode transistor, gate is connected to |
| A. | Vdd |
| B. | source |
| C. | ground |
| D. | drain |
| Answer» C. ground | |
| 18. |
The allowable output voltage is limited by |
| A. | load resistance |
| B. | load capacitance |
| C. | barreir height |
| D. | material used for barrier |
| Answer» D. material used for barrier | |
| 19. |
Inverter uses D-MESFET as |
| A. | load |
| B. | switching device |
| C. | controller |
| D. | amplifier |
| Answer» B. switching device | |