Why can a synchronous counter operate at a higher frequency than a ripple counter?

A synchronous counter cannot operate at higher frequencies.

The flip-flops change one after the other.

The flip-flops change at the same time.

A synchronous counter cannot operate at higher frequencies.

Which of the following groups of logic devices would be the minimum required for a MOD-64 synchronous counter?

Five flip-flops, three AND gates

Seven flip-flops, five AND gates

The designation means that the ________.

up count is active-LOW, the down count is active-HIGH

up count is active-HIGH, the down count is active-LOW

up count is active-LOW, the down count is active-HIGH

up and down counts are both active-LOW

up and down counts are both active-HIGH

What is the difference between a 7490 and a 7493?

7490 is a MOD-16, 7493 is a MOD-10

7490 is a MOD-10, 7493 is a MOD-16

7490 is a MOD-16, 7493 is a MOD-10

7490 is a MOD-12, 7493 is a MOD-16

7490 is a MOD-10, 7493 is a MOD-12

What function does the CTR DIV 8 circuit given below perform?

It divides the clock frequency down to match the frequency of the serial data in.

The divide-by-8 counter is triggered by the control flip-flop and clock, which then allows the data output register to begin storing the input data. Once all eight data bits are stored in the data output register, the data output register and the divide-by-8 counter trigger the one-shot. The one-shot then begins the process all over again.

The divide-by-8 counter is used to verify that the parity bit is attached to the input data string.

It keeps track of the eight data bits, triggering the transfer of the data through the output register and the one-shot, which then resets the control flip-flop and divide-by-8 counter.

Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:

input clock pulses are not used to activate any of the counter stages.

input clock pulses are applied only to the first and last stages.

input clock pulses are applied only to the last stage.

input clock pulses are applied simultaneously to each stage.

input clock pulses are not used to activate any of the counter stages.

In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs?

The counter is not zero and we need to count down by one.

A trigger edge has occurred and we must load the counter.

The counter is zero and we need to keep it at zero.

The counter is not zero and we need to count down by one.

A seven-segment, common-anode LED display is designed for:

disorientation of segment modules

all cathodes to be wired together

a HIGH to turn off each segment

disorientation of segment modules

To operate correctly, starting a ring counter requires:

clearing one flip-flop and presetting all the others.

presetting one flip-flop and clearing all the others.

How many AND gates would be required to completely decode ALL the states of a MOD-64 counter, and how many inputs must each AND gate have?

128 gates, 5 inputs to each gate

128 gates, 6 inputs to each gate

64 gates, 5 inputs to each gate

64 gates, 6 inputs to each gate

128 gates, 5 inputs to each gate

One of the major drawbacks to the use of asynchronous counters is:

asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications

low-frequency applications are limited because of internal propagation delays

high-frequency applications are limited because of internal propagation delays

asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications

asynchronous counters do not have propagation delays and this limits their use in high-frequency applications

How can the active condition (HIGH or LOW) or the decoder output be determined from the logic symbol?

A square indicates active-HIGH.

A bubble indicates active-HIGH.

A square indicates active-HIGH.

In a BCD-to-seven-segment converter, why must a code converter be utilized?

to convert the 4-bit BCD into 10-bit code

to convert the 4-bit BCD into 7-bit code

to convert the 4-bit BCD into 10-bit code

to convert the 4-bit BCD into Gray code

A microcontroller differs from a microprocessor in that it has several ________ ports and ________ built into its architecture, making it better suited for ________ applications.

parallel, logic gates, processing

Why is the Gray code more practical to use when coding the position of a rotating shaft?

All digits change between counts.

Two digits change between counts.

Only one digit changes between counts.

2291 + Mcqs in Digital Electronics in Engineering Page 8 McqOptions

351.	Which of the following is an example of a counter with a truncated modulus?
A.	8
B.	13
C.	16
D.	32
Answer» C. 16

352.	Why can a synchronous counter operate at a higher frequency than a ripple counter?
A.	The flip-flops change one after the other.
B.	The flip-flops change at the same time.
C.	A synchronous counter cannot operate at higher frequencies.
D.	A ripple counter is faster.
Answer» C. A synchronous counter cannot operate at higher frequencies.

353.	Which of the following is a type of shift register counter?
A.	Decade
B.	Binary
C.	Ring
D.	BCD
Answer» D. BCD

354.	Which of the following groups of logic devices would be the minimum required for a MOD-64 synchronous counter?
A.	Five flip-flops, three AND gates
B.	Seven flip-flops, five AND gates
C.	Four flip-flops, ten AND gates
D.	Six flip-flops, four AND gates
Answer» E.

355.	How many data bits can be stored in the register shown below?
A.	5
B.	32
C.	31
D.	4
Answer» B. 32

356.	The designation means that the ________.
A.	up count is active-HIGH, the down count is active-LOW
B.	up count is active-LOW, the down count is active-HIGH
C.	up and down counts are both active-LOW
D.	up and down counts are both active-HIGH
Answer» B. up count is active-LOW, the down count is active-HIGH

357.	For a one-shot application, how can HDL code be used to make a circuit respond once to each positive transition on its trigger input?
A.	By using a counter
B.	By using an active clock
C.	By using an immediate reload
D.	By using edge trapping
Answer» E.

358.	A counter with a modulus of 16 acts as a ________.
A.	divide-by-8 counter
B.	divide-by-16 counter
C.	divide-by-32 counter
D.	divide-by-64 counter
Answer» C. divide-by-32 counter

359.	What is the difference between a 7490 and a 7493?
A.	7490 is a MOD-10, 7493 is a MOD-16
B.	7490 is a MOD-16, 7493 is a MOD-10
C.	7490 is a MOD-12, 7493 is a MOD-16
D.	7490 is a MOD-10, 7493 is a MOD-12
Answer» B. 7490 is a MOD-16, 7493 is a MOD-10

360.	What function does the CTR DIV 8 circuit given below perform?
A.	It divides the clock frequency down to match the frequency of the serial data in.
B.	The divide-by-8 counter is triggered by the control flip-flop and clock, which then allows the data output register to begin storing the input data. Once all eight data bits are stored in the data output register, the data output register and the divide-by-8 counter trigger the one-shot. The one-shot then begins the process all over again.
C.	The divide-by-8 counter is used to verify that the parity bit is attached to the input data string.
D.	It keeps track of the eight data bits, triggering the transfer of the data through the output register and the one-shot, which then resets the control flip-flop and divide-by-8 counter.
Answer» E.

361.	Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:
A.	input clock pulses are applied only to the first and last stages.
B.	input clock pulses are applied only to the last stage.
C.	input clock pulses are applied simultaneously to each stage.
D.	input clock pulses are not used to activate any of the counter stages.
Answer» D. input clock pulses are not used to activate any of the counter stages.

362.	A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state does the counter go on the next clock pulse?
A.	1101
B.	1011
C.	1111
D.	0000
Answer» C. 1111

364.	The terminal count of a 3-bit binary counter in the DOWN mode is ________.
A.	000
B.	111
C.	101
D.	010
Answer» B. 111

365.	The hexadecimal equivalent of 15,536 is ________.
A.	3CB0
B.	3C66
C.	63C0
D.	6300
Answer» B. 3C66

367.	Which of the following is an invalid output state for an 8421 BCD counter?
A.	1110
B.	0000
C.	0010
D.	0001
Answer» B. 0000

363.	A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________.
A.	15 ns
B.	30 ns
C.	45 ns
D.	60 ns
Answer» E.

366.	In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs?
A.	A trigger edge has occurred and we must load the counter.
B.	The counter is zero and we need to keep it at zero.
C.	The shift register is reset.
D.	The counter is not zero and we need to count down by one.
Answer» D. The counter is not zero and we need to count down by one.

368.	How many different states does a 3-bit asynchronous counter have?
A.	2
B.	4
C.	8
D.	16
Answer» D. 16

369.	How many flip-flops are required to construct a decade counter?
A.	10
B.	8
C.	5
D.	4
Answer» E.

370.	The terminal count of a typical modulus-10 binary counter is ________.
A.	0000
B.	1010
C.	1001
D.	1111
Answer» D. 1111

371.	A seven-segment, common-anode LED display is designed for:
A.	all cathodes to be wired together
B.	one common LED
C.	a HIGH to turn off each segment
D.	disorientation of segment modules
Answer» D. disorientation of segment modules

372.	To operate correctly, starting a ring counter requires:
A.	clearing one flip-flop and presetting all the others.
B.	clearing all the flip-flops.
C.	presetting one flip-flop and clearing all the others.
D.	presetting all the flip-flops.
Answer» D. presetting all the flip-flops.

373.	When two counters are cascaded, the overall MOD number is equal to the ________ of their individual MOD numbers.
A.	product
B.	sum
C.	log
D.	reciprocal
Answer» B. sum

374.	A MOD-12 and a MOD-10 counter are cascaded. Determine the output frequency if the input clock frequency is 60 MHz.
A.	500 kHz
B.	1,500 kHz
C.	6 MHz
D.	5 MHz
Answer» B. 1,500 kHz

375.	How many natural states will there be in a 4-bit ripple counter?
A.	4
B.	8
C.	16
D.	32
Answer» D. 32

Explore topic-wise MCQs in Engineering.

Which of the following is an example of a counter with a truncated modulus?

Why can a synchronous counter operate at a higher frequency than a ripple counter?

Which of the following is a type of shift register counter?

Which of the following groups of logic devices would be the minimum required for a MOD-64 synchronous counter?

How many data bits can be stored in the register shown below?

The designation means that the ________.

For a one-shot application, how can HDL code be used to make a circuit respond once to each positive transition on its trigger input?

A counter with a modulus of 16 acts as a ________.

What is the difference between a 7490 and a 7493?

What function does the CTR DIV 8 circuit given below perform?

Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:

A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state does the counter go on the next clock pulse?

A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________.

The terminal count of a 3-bit binary counter in the DOWN mode is ________.

The hexadecimal equivalent of 15,536 is ________.

In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs?

Which of the following is an invalid output state for an 8421 BCD counter?

How many different states does a 3-bit asynchronous counter have?

How many flip-flops are required to construct a decade counter?

The terminal count of a typical modulus-10 binary counter is ________.

A seven-segment, common-anode LED display is designed for:

To operate correctly, starting a ring counter requires:

When two counters are cascaded, the overall MOD number is equal to the ________ of their individual MOD numbers.

A MOD-12 and a MOD-10 counter are cascaded. Determine the output frequency if the input clock frequency is 60 MHz.

How many natural states will there be in a 4-bit ripple counter?

A ripple counter's speed is limited by the propagation delay of:

Referring to the given figure, at which point is the serial data transferred to the parallel output?

How many AND gates would be required to completely decode ALL the states of a MOD-64 counter, and how many inputs must each AND gate have?

A 4-bit counter has a maximum modulus of ________.

What function will the counter shown below be performing during period "B" on the timing diagram?

Three cascaded decade counters will divide the input frequency by ________.

One of the major drawbacks to the use of asynchronous counters is:

The final output of a modulus-8 counter occurs one time for every ________.

Once an up-/down-counter begins its count sequence, it cannot be reversed.

Three cascaded modulus-5 counters have an overall modulus of ________.

An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required?

A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(tot)) is ________.

A four-channel scope is used to check the counter in the figure given below. Are the displayed waveforms correct?

One application of a digital multiplexer is to facilitate:

How can the active condition (HIGH or LOW) or the decoder output be determined from the logic symbol?

If two inputs are active on a priority encoder, which will be coded on the output?

A circuit that responds to a specific set of signals to produce a related digital signal output is called a(n):

How many 74184 BCD-to-binary converters would be required to convert two complete BCD digits to a binary number?

How many select lines would be required for an 8-line-to-1-line multiplexer?

A binary code that progresses such that only one bit changes between two successive codes is:

Which of the following is not a weighted value positional numbering system:

In a BCD-to-seven-segment converter, why must a code converter be utilized?

A microcontroller differs from a microprocessor in that it has several ________ ports and ________ built into its architecture, making it better suited for ________ applications.

A truth table with output columns numbered 0 15 may be for which type of decoder IC?

Why is the Gray code more practical to use when coding the position of a rotating shaft?

A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (t_p(tot)) is ________.

A microcontroller differs from a microprocessor in that it has several ports and built into its architecture, making it better suited for applications.

376.	A ripple counter's speed is limited by the propagation delay of:
A.	each flip-flop
B.	all flip-flops and gates
C.	the flip-flops only with gates
D.	only circuit gates
Answer» B. all flip-flops and gates

377.	Referring to the given figure, at which point is the serial data transferred to the parallel output?
A.	W
B.	X
C.	Y
D.	Z
Answer» E.

378.	How many AND gates would be required to completely decode ALL the states of a MOD-64 counter, and how many inputs must each AND gate have?
A.	128 gates, 6 inputs to each gate
B.	64 gates, 5 inputs to each gate
C.	64 gates, 6 inputs to each gate
D.	128 gates, 5 inputs to each gate
Answer» D. 128 gates, 5 inputs to each gate

379.	A 4-bit counter has a maximum modulus of ________.
A.	3
B.	6
C.	8
D.	16
Answer» E.

380.	What function will the counter shown below be performing during period "B" on the timing diagram?
A.	Counting up
B.	Counting down
C.	Inhibited
D.	Loading
Answer» B. Counting down

381.	Three cascaded decade counters will divide the input frequency by ________.
A.	10
B.	20
C.	100
D.	1,000
Answer» E.

382.	One of the major drawbacks to the use of asynchronous counters is:
A.	low-frequency applications are limited because of internal propagation delays
B.	high-frequency applications are limited because of internal propagation delays
C.	asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications
D.	asynchronous counters do not have propagation delays and this limits their use in high-frequency applications
Answer» C. asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications

383.	The final output of a modulus-8 counter occurs one time for every ________.
A.	8 clock pulses
B.	16 clock pulses
C.	24 clock pulses
D.	32 clock pulses
Answer» B. 16 clock pulses

384.	Once an up-/down-counter begins its count sequence, it cannot be reversed.
A.	True
B.	False
Answer» C.

385.	Three cascaded modulus-5 counters have an overall modulus of ________.
A.	5
B.	25
C.	125
D.	500
Answer» D. 500