Explore topic-wise MCQs in Engineering.

If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?

The circuit given below fails to function; the inputs are checked with a logic probe and the following indications are obtained: CLK, J1, J2, J3, K1, K2, and K3 are pulsing. Q and are HIGH. and PRE are LOW. What could be causing the problem?

Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock input.

Which is not a real advantage of HDL?

Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________.

Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

Edge-triggered flip-flops must have:

In VHDL, how is each instance of a component addressed?

The logic gate that will have HIGH or "1" at its output when any one of its inputs is HIGH is a(n):

Which of the symbols shown below represents an AND gate?

For a three-input AND gate, with the input waveforms as shown below, which output waveform is correct?

The special software application that translates from HDL into a grid of 1's and 0's, which can be loaded into a PLD, is called a:

As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:

A positive edge-triggered D flip-flop will store a 1 when ________.

If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?

Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (f_in) to the first flip-flop is 32 kHz, the output frequency (f_out) is ________.

A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?

The output of a gated S-R flip-flop changes only if the:

Simplify the expression using DeMorgan's theorems.

To completely load and then unload an 8-bit register requires how many clock pulses?

What is one disadvantage of an S-R flip-flop?

Which of the following best describes the action of pulse-triggered FF's?

An invalid condition in the operation of an active-HIGH input S-R latch occurs when ________.

For a three-input NOR gate, with the input waveforms as shown below, which output waveform is correct?

What is the indication of a short to ground in the output of a driving gate?

What will a design engineer do after he/she is satisfied that the design will work?

In VHDL, macrofunctions is/are:

Which of the following is an important feature of the sum-of-products form of expressions?

An output gate is connected to four input gates; the circuit does not function. Preliminary tests with the DMM indicate that the power is applied; scope tests show that the primary input gate has a pulsing signal, while the interconnecting node has no signal. The four load gates are all on different ICs. Which instrument will best help isolate the problem?

What is the indication of a short on the input of a load gate?

In HDL, LITERALS is/are:

Which of the K-maps given below represents the expression X = AC + BC + B?

A decoder can be used as a demultiplexer by ________.

How many 4-bit parallel adders would be required to add two binary numbers each representing decimal numbers up through 300₁₀?

Which statement below best describes a Karnaugh map?

Each "1" entry in a K-map square represents:

For a two-input XNOR gate, with the input waveforms as shown below, which output waveform is correct?

A certain BCD-to-decimal decoder has active-HIGH inputs and active-LOW outputs. Which output goes LOW when the inputs are 1001?

What type of logic circuit is represented by the figure shown below?

What is the difference between an astable multivibrator and a monostable multivibrator?

Is there any limit to the number of times that a 74123 can be retriggered?

The Ex-NOR is sometimes called the ________.

Parity systems are defined as either________ or ________ and will add an extra ________ to the digital information being transmitted.

Which type of gate can be used to add two bits?

Why is an exclusive-NOR gate also called an equality gate?

Pulse stretching, time-delay, and pulse generation are all easily accomplished with which type of multivibrator circuit?

The internal circuitry of the 555 timer consists of ________, an R-S flip-flop, a transistor switch, an output buffer amplifier, and a voltage divider.

With most monostable multivibrators, what is the Q output when no input trigger has occurred?

The output of the astable circuit ________.

If a diode is connected across resistor R_B (positive end up) in the given figure, what is the new duty cycle of the output waveform?