Explore topic-wise MCQs in Engineering.

The problem of interfacing IC logic families that have different supply voltages (V_CC's) can be solved by using a:

The term buffer/driver signifies the ability to provide low output currents to drive light loads.

Why is the operating frequency for CMOS devices critical for determining power dissipation?

The problem of different current requirements when CMOS logic circuits are driving TTL logic circuits can usually be overcome by the addition of:

Which family of devices has the characteristic of preventing saturation during operation?

How many 74LSTTL logic gates can be driven from a 74TTL gate?

From the following specifications determine the fan-out for the logic family.

CLB is the acronym for ________.

What can the GAL22V10 do that the GAL16V8 cannot?

The output of this circuit is always ________.

By adding an OR gate to a simple programmable logic device (SPLD) the foundation for a(n) ________ is made possible.

Now many times can a GAL be erased and reprogrammed?

Which of the following increases the number of product terms by borrowing unused product from other macrocells?

MPGA stands for:

Which of the figures shown below represents the exclusive-NOR gate?

For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be LOW. What is the status of the Y output?

Which of the circuits in figure (a to d) is the sum-of-products implementation of figure (e)?

For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be HIGH. What is the status of the Y output?

Gated S-R flip-flops are called asynchronous because the output responds immediately to input changes.

Which of the following is not generally associated with flip-flops?

What is one disadvantage of an S-R flip-flop?

Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?

The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the:

With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?

One example of the use of an S-R flip-flop is as a(n):

A J-K flip-flop is in a "no change" condition when ________.

What is the difference between the 7476 and the 74LS76?

Which is not an Altera primitive port identifier?

The timing network that sets the output frequency of a 555 astable circuit contains ________.

MOD-6 and MOD-12 counters and multiples are most commonly used as:

Which of the following is an invalid state in an 8421 BCD counter?

After 10 clock cycles, and assuming that the DATA input had returned to 0 following the storage sequence, what values would be stored in Q4, Q3, Q2, Q1, Q0 of the register in Figure 7-5?

How many different states does a 2-bit asynchronous counter have?

Which of the following statements are true?

A principle regarding most display decoders is that when the correct input is present, the related output will switch:

A modulus-10 counter must have ________.

What type of device is shown below?

What does the triangle on the clock input of a J-K flip-flop mean?

A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.

The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________.

Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.

A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:

How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?

What is the difference between the enable input of the 7475 and the clock input of the 7474?

The phenomenon of interpreting unwanted signals on J and K while C_p (clock pulse) is HIGH is called ________.

What is another name for a one-shot?

On a master-slave flip-flop, when is the master enabled?

A 12 MHz clock frequency is applied to a cascaded counter containing a modulus-5 counter, a modulus-8 counter, and a modulus-10 counter. The lowest output frequency possible is ________.

A multiplexed display being driven by a logic circuit:

What is meant by parallel load of a counter?