MCQOPTIONS
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MCQOPTIONS
This section includes 2291 Mcqs, each offering curated multiple-choice questions to sharpen your Engineering knowledge and support exam preparation. Choose a topic below to get started.
| 201. |
Which of the figures given below represents a NAND gate?
|
| A. | a |
| B. | b |
| C. | c |
| D. | d |
| Answer» B. b | |
| 202. |
A NOR gate with one HIGH input and one LOW input: |
| A. | will output a HIGH |
| B. | functions as an AND |
| C. | will not function |
| D. | will output a LOW |
| Answer» E. | |
| 203. |
Special handling precautions should be taken when working with MOS devices. Which of the following statements is not one of these precautions? |
| A. | All test equipment should be grounded. |
| B. | MOS devices should have their leads shorted together for shipment and storage. |
| C. | Never remove or insert MOS devices with the power on. |
| D. | Workers handling MOS devices should not have grounding straps attached to their wrists. |
| Answer» E. | |
| 204. |
Why must CMOS devices be handled with care? |
| A. | so they don t get dirty |
| B. | because they break easily |
| C. | because they can be damaged by static electricity discharge |
| Answer» D. | |
| 205. |
Which of the figures given below represents an OR gate?
|
| A. | a |
| B. | b |
| C. | c |
| D. | d |
| Answer» B. b | |
| 206. |
How many outputs are on a BCD decoder? |
| A. | 4 |
| B. | 16 |
| C. | 8 |
| D. | 10 |
| Answer» E. | |
| 207. |
Which digital system translates coded characters into a more useful form? |
| A. | encoder |
| B. | display |
| C. | counter |
| D. | decoder |
| Answer» E. | |
| 208. |
In a Gray code, each number is 3 greater than the binary representation of that number. |
| A. | True |
| B. | False |
| Answer» C. | |
| 209. |
Use the weighting factors to convert the following BCD numbers to binary. 0101 0011 0010 0110 1000 |
| A. | 01010011 001001101000 |
| B. | 11010100 100001100000 |
| C. | 110101 100001100 |
| D. | 101011 001100001 |
| Answer» D. 101011 001100001 | |
| 210. |
How many flip-flops are required to make a MOD-32 binary counter? |
| A. | 3 |
| B. | 45 |
| C. | 5 |
| D. | 6 |
| Answer» D. 6 | |
| 211. |
Using four cascaded counters with a total of 16 bits, how many states must be deleted to achieve a modulus of 50,000? |
| A. | 50,000 |
| B. | 65,536 |
| C. | 25,536 |
| D. | 15,536 |
| Answer» E. | |
| 212. |
The terminal count of a modulus-11 binary counter is ________. |
| A. | 1010 |
| B. | 1000 |
| C. | 1001 |
| D. | 1100 |
| Answer» B. 1000 | |
| 213. |
List which pins need to be connected together on a 7493 to make a MOD-12 counter. |
| A. | 12 to 1, 11 to 3, 9 to 2 |
| B. | 12 to 1, 11 to 3, 12 to 2 |
| C. | 12 to 1, 11 to 3, 8 to 2 |
| D. | 12 to 1, 11 to 3, 1 to 2 |
| Answer» D. 12 to 1, 11 to 3, 1 to 2 | |
| 214. |
Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz. |
| A. | 10.24 kHz |
| B. | 5 kHz |
| C. | 30.24 kHz |
| D. | 15 kHz |
| Answer» C. 30.24 kHz | |
| 215. |
Propagation delay time, tPLH, is measured from the ________. |
| A. | triggering edge of the clock pulse to the LOW-to-HIGH transition of the output |
| B. | triggering edge of the clock pulse to the HIGH-to-LOW transition of the output |
| C. | preset input to the LOW-to-HIGH transition of the output |
| D. | clear input to the HIGH-to-LOW transition of the output |
| Answer» B. triggering edge of the clock pulse to the HIGH-to-LOW transition of the output | |
| 216. |
How many flip-flops are in the 7475 IC? |
| A. | 1 |
| B. | 2 |
| C. | 4 |
| D. | 8 |
| Answer» D. 8 | |
| 217. |
How many flip-flops are required to produce a divide-by-128 device? |
| A. | 1 |
| B. | 4 |
| C. | 6 |
| D. | 7 |
| Answer» E. | |
| 218. |
The format used to present the logic output for the various combinations of logic inputs to a gate is called a(n): |
| A. | truth table. |
| B. | input logic function. |
| C. | Boolean constant. |
| D. | Boolean variable. |
| Answer» B. input logic function. | |
| 219. |
For a three-input OR gate, with the input waveforms as shown below, which output waveform is correct?
|
| A. | a |
| B. | b |
| C. | c |
| D. | d |
| Answer» C. c | |
| 220. |
Which of the figures given below represents a NOR gate?
|
| A. | a |
| B. | b |
| C. | c |
| D. | d |
| Answer» E. | |
| 221. |
A small circle on the output of a logic gate is used to represent the: |
| A. | Comparator operation. |
| B. | OR operation. |
| C. | NOT operation. |
| D. | AND operation. |
| Answer» D. AND operation. | |
| 222. |
What is the basic difference between AHDL and VHDL? |
| A. | ADHL is used in all PLD's. |
| B. | VHDL is used in all PLD's. |
| C. | ADHL is proprietary. |
| D. | VHDL is proprietary. |
| Answer» D. VHDL is proprietary. | |
| 223. |
What is the input/output pin configuration of the GAL22V10? |
| A. | 10 output pins and 12 input pins |
| B. | 2 special-purpose pins |
| C. | 8 pins that are either inputs or outputs |
| D. | All of the above |
| Answer» B. 2 special-purpose pins | |
| 224. |
What gives a GAL its flexibility? |
| A. | Its speed |
| B. | Its reprogrammable EPROM |
| C. | Its large logic arrays |
| D. | Its programmable OLMCs |
| Answer» E. | |
| 225. |
What is the status of a tristate output buffer on a MAX7000S family device? |
| A. | It is permanently enabled or disabled. |
| B. | It is controlled by one of the two global output enable pins. |
| C. | It is controlled by other inputs or functions generated by other macrocells. |
| D. | All of the above |
| Answer» E. | |
| 226. |
GAL is an acronym for ________. |
| A. | Generic Array Logic |
| B. | General Array Logic |
| C. | Giant Array Logic |
| D. | Generic Analysis Logic |
| Answer» B. General Array Logic | |
| 227. |
What does a dot mean when placed on a PLD circuit diagram? |
| A. | A point that is programmable |
| B. | A point that cannot change |
| C. | An intersection of logic blocks |
| D. | An input or output point |
| Answer» C. An intersection of logic blocks | |
| 228. |
FPGA is the acronym for ________. |
| A. | Flexible Programming [of] Generic Assemblies |
| B. | Field Programmable Generic Array |
| C. | Field Programmable Gate Array |
| D. | Field Programmer's Gate Assembly |
| Answer» D. Field Programmer's Gate Assembly | |
| 229. |
Which of the following testing procedures uses the JTAG IEEE standard? |
| A. | Bed-of-nails |
| B. | Flying probe |
| C. | EXTEST |
| D. | Boundary scan |
| Answer» E. | |
| 230. |
How many combinations are handled in an LUT? |
| A. | 4 |
| B. | 8 |
| C. | 16 |
| D. | 32 |
| Answer» D. 32 | |
| 231. |
The content of a simple programmable logic device (PLD) consists of: |
| A. | fuse-link arrays |
| B. | thousands of basic logic gates |
| C. | advanced sequential logic functions |
| D. | thousands of basic logic gates and advanced sequential logic functions |
| Answer» E. | |
| 232. |
Field-programmable gate arrays (FGPAs) use ________ memory technology, which is ________. |
| A. | DRAM, nonvolatile |
| B. | SRAM, nonvolatile |
| C. | SRAM, volatile |
| D. | RAM, volatile |
| Answer» D. RAM, volatile | |
| 233. |
The macrocells in a PAL/GAL are located ________. |
| A. | after the programmable AND arrays |
| B. | ahead of the programmable AND arrays |
| C. | at the input terminals |
| D. | at the output terminals |
| Answer» B. ahead of the programmable AND arrays | |
| 234. |
A PAL16L8 has: |
| A. | 10 inputs and 8 outputs. |
| B. | 8 inputs and 8 outputs. |
| C. | 16 inputs and 16 outputs. |
| D. | 16 inputs and 8 outputs. |
| Answer» B. 8 inputs and 8 outputs. | |
| 235. |
Which is a major digital system category? |
| A. | Standard logic devices |
| B. | ASICs |
| C. | Microprocessor/DSP devices |
| D. | All of the above |
| Answer» E. | |
| 236. |
What does the Altera FLEX10K PLD use in place of AND and OR arrays? |
| A. | Nothing, it uses AND and OR arrays. |
| B. | Look-up tables |
| C. | SRAM-based memory |
| D. | HPLD architecture |
| Answer» C. SRAM-based memory | |
| 237. |
PIA is an acronym for ________. |
| A. | Programmable Interface Array |
| B. | Post Integrated Array |
| C. | Programmable Input Array |
| D. | Programmable Interconnect Array |
| Answer» E. | |
| 238. |
Which one of the following is an embedded function of the Stratix II FPGA? |
| A. | AND-OR logic |
| B. | Programmable SOP |
| C. | Digital signal processing |
| D. | None of the above |
| Answer» D. None of the above | |
| 239. |
When is a level-shifter circuit needed in interfacing logic? |
| A. | A level shifter is always needed. |
| B. | A level shifter is never needed. |
| C. | when the supply voltages are the same |
| D. | when the supply voltages are different |
| Answer» E. | |
| 240. |
Which of the following testing procedures has one or more external moving parts? |
| A. | Bed-of-nails |
| B. | Flying probe |
| C. | EXTEST |
| D. | Boundary scan |
| Answer» C. EXTEST | |
| 241. |
In an OLMC, where does the FMUX signal go? |
| A. | OMUX |
| B. | D flip-flop |
| C. | Matrix |
| D. | PAL |
| Answer» D. PAL | |
| 242. |
FPLA is: |
| A. | a nonmemory programmable device. |
| B. | a programmable AND array. |
| C. | a programmable OR array. |
| D. | All of the above |
| Answer» E. | |
| 243. |
A(n) ________ is a section of embedded logic that is commonly found in FPGAs. |
| A. | LUT |
| B. | core |
| C. | DSP |
| D. | PI |
| Answer» C. DSP | |
| 244. |
In a FLEX10K, what two outputs will the LE produce? |
| A. | The LAB and the fast track |
| B. | ON and OFF |
| C. | Hi-Z and ON |
| D. | Hi-Z and OFF |
| Answer» B. ON and OFF | |
| 245. |
ASIC stands for: |
| A. | advanced speed integrated circuit. |
| B. | advanced standard integrated circuit. |
| C. | application specific integrated circuit. |
| D. | application speedy integrated circuit. |
| Answer» D. application speedy integrated circuit. | |
| 246. |
What is the major downfall of microprocessor/DSP systems? |
| A. | Speed they are too fast |
| B. | Speed they are too slow |
| C. | Too much flexibility |
| D. | Not enough flexibility |
| Answer» C. Too much flexibility | |
| 247. |
What should be done with unused inputs to a TTL NAND gate? |
| A. | let them float |
| B. | tie them LOW |
| C. | tie them HIGH |
| Answer» D. | |
| 248. |
How does the 4000 series of CMOS logic compare in terms of speed and power dissipation to the standard family of TTL logic? |
| A. | more power dissipation and slower speed |
| B. | more power dissipation and faster speed |
| C. | less power dissipation and faster speed |
| D. | less power dissipation and slower speed |
| Answer» E. | |
| 249. |
What is the standard TTL noise margin? |
| A. | 5.0 V |
| B. | 0.0 V |
| C. | 0.8 V |
| D. | 0.4 V |
| Answer» E. | |
| 250. |
How can ECL have both a NOR and an OR output? |
| A. | ECL does not have this feature. |
| B. | They are simply the inverse of each other. |
| Answer» C. | |
