MCQOPTIONS
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MCQOPTIONS
This section includes 103 Mcqs, each offering curated multiple-choice questions to sharpen your Electrical Engineering knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
(1(10101)2 is_______________? |
| A. | (37)10 |
| B. | ( 69)10 |
| C. | (41 )10 |
| D. | — (5)10 |
| Answer» B. ( 69)10 | |
| 2. |
In figure, R = 20KΩ and C = 75 pF. The converter clock frequency will be |
| A. | 606 Hz |
| B. | 1212 Hz |
| C. | 555 KHz |
| D. | 606 KHz |
| Answer» B. 1212 Hz | |
| 3. |
figure shows three pulse train inputs to a 3-input OR gate. Assuming positive logic, the output pulse rate train in figure (b) would be |
| A. | [A]. |
| B. | [B]. |
| C. | [C]. |
| D. | [D]. |
| Answer» D. [D]. | |
| 4. |
figure shows three pulse train inputs to a 3-input AND gate. Assuming positive logic, the output signal obtained in figure would be |
| A. | [A]. |
| B. | [B]. |
| C. | [C]. |
| D. | [D]. |
| Answer» C. [C]. | |
| 5. |
For a D/A converter, inputs and outputs are given. The output corresponding to digital input 01000 |
| A. | 2.0 V |
| B. | 2.5 V |
| C. | 3.0 V |
| D. | 4.0 V |
| Answer» B. 2.5 V | |
| 6. |
Assume that only x and y logic inputs are available. What is the minimum number of 2-input NAND gates required to implement x ⊕ y? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» D. 5 | |
| 7. |
In a digital system, the maximum clock frequency that can be used with Master/Slave Clocked flip-flops having total propagation delay of 200 μsec is |
| A. | 20 MHz |
| B. | 50 MHz |
| C. | 100 MHz |
| D. | 200 MHz |
| Answer» C. 100 MHz | |
| 8. |
The ASCII code is for information interchange by a binary code for |
| A. | alphabet only |
| B. | number only |
| C. | alpha-numeric and other common symbols |
| D. | none of these |
| Answer» D. none of these | |
| 9. |
The PC contains 0450 H and SP contains 08D 6 H. What will be content of P and SP following a CALL to subroutine at location 02 AFH? |
| A. | 0453 H, 08 D 8 H |
| B. | 0453 H, 08 D 4 H |
| C. | 02 AFH, 08 D 8 H |
| D. | 02 AFH, 08 D 4 H |
| Answer» E. | |
| 10. |
What is the memory word size of 8085 μp? |
| A. | 6 bits |
| B. | 8 bits |
| C. | 12 bits |
| D. | 16 bits |
| Answer» C. 12 bits | |
| 11. |
A clock pulse is fed into 3 bit binary down count. The signal at B output is |
| A. | [A]. |
| B. | [B]. |
| C. | [C]. |
| D. | none of these |
| Answer» B. [B]. | |
| 12. |
If tp is the pulse width, Δt is the propagation delay, T is period of pulse train then the following condition can avoid the race around condition |
| A. | tp = Δt = T |
| B. | 2tp > Δt > T |
| C. | tp < Δt < T |
| D. | tp < Δt < T |
| Answer» D. tp < Δt < T | |
| 13. |
In number system e.g. 6, a “decade” counter has to recycle to 0 at the sixth count. Which of the connections indicate below will realize this resetting? (a logic “0” at the R inputs resets the counters) |
| A. | [A]. |
| B. | [B]. |
| C. | [C]. |
| D. | None of these |
| Answer» D. None of these | |
| 14. |
Given two numbers A and B in sign magnitude representation in an eight bit format A = 00011110 and B = 10011100 then A ⊕ B gives |
| A. | 10000010 |
| B. | 00011111 |
| C. | 10011101 |
| D. | 11100001 |
| Answer» B. 00011111 | |
| 15. |
What is the length of SP (Stack pointer) of 8085 μp? |
| A. | 6 bits |
| B. | 8 bits |
| C. | 12 bits |
| D. | 16 bits |
| Answer» E. | |
| 16. |
How many lines are there in address bus of 8085 μp? |
| A. | 6 |
| B. | 8 |
| C. | 12 |
| D. | 16 |
| Answer» E. | |
| 17. |
How many input-output ports can be accessed by direct method of 8085 μp? |
| A. | 8 |
| B. | 256 |
| C. | 32 K |
| D. | 64 K |
| Answer» C. 32 K | |
| 18. |
How many interrupts are there of 8085 μP? |
| A. | 4 |
| B. | 5 |
| C. | 6 |
| D. | 8 |
| Answer» C. 6 | |
| 19. |
The binary number 0.10110111101 is equal to hexadecimal number |
| A. | B3A |
| B. | B5A |
| C. | B7A |
| D. | BA7 |
| Answer» D. BA7 | |
| 20. |
For the following decimal multiplication the result are given in binary numbers, Spot the incorrect relation, if any |
| A. | 15 x 3 = 110000112 |
| B. | 42 x 1/12 = 10011.1102 |
| C. | 7.75 x 2.5 = 10011.1102 |
| D. | [D]. |
| Answer» E. | |
| 21. |
Square root of 4 is |
| A. | (16)16 |
| B. | (2)2 |
| C. | (8)16 |
| D. | (5)16 |
| Answer» E. | |
| 22. |
Consider the following instruction of 8085 μp :MOV M, AAODCMVI A, FFCMP M Which of these cause change in the status of flag(s)? |
| A. | 1 and 2 |
| B. | 1, 2 and 3 |
| C. | 3 and 4 |
| D. | 2 and 4 |
| Answer» E. | |
| 23. |
Consider the following registers: A accumulator and B registerB and C registersD and E registersH and L registers Which of these 8-bit registers of 8085 μP can be paired together to make a 16-bit register? |
| A. | 1, 3 and 4 |
| B. | 2, 3 and 4 |
| C. | 1 and 2 |
| D. | 1, 2 and 3 |
| Answer» C. 1 and 2 | |
| 24. |
F's complement of (2BFD)hex is |
| A. | E 304 |
| B. | D 403 |
| C. | D 402 |
| D. | C 403 |
| Answer» D. C 403 | |
| 25. |
To have the multiprocessing capabilities of the 8086 microprocessor, the pin connected to the ground is |
| A. | DEN |
| B. | ALE |
| C. | INTER |
| D. | [D]. |
| Answer» E. | |
| 26. |
The following program starts at location 0100HL X ISP, 00FF - the content if accumulatorLXIH, 0701 - when the program counterMVI A, 20 H - reaches 0109 H is S ∪ BM |
| A. | 20 H |
| B. | 02 H |
| C. | 00 H |
| D. | FFH |
| Answer» B. 02 H | |
| 27. |
The circuit show in the figure has 4 boxes each described by inputs P, Q, R and outputs y, z withY = P ⊕ Q ⊕ R, Z = RQ + PR + QP The circuit act as a |
| A. | 4 bit adder giving P + Q |
| B. | 4 bit subtractor P - Q |
| C. | 4 bit subtractor Q - P |
| D. | 4 bit adder P + Q + R |
| Answer» C. 4 bit subtractor Q - P | |
| 28. |
Consider the following statements in connection with CMOS inverter in figure where both the MOSFET are of enhancement type and both have a threshold voltage of 2 Vstatements 1: T1 conducts when vi ≥ 2 Vstatements 2: T1 is always in saturation when v0 = 0 VWhich of the following is correct? |
| A. | Only statement 1 is true |
| B. | Only statement 2 is true |
| C. | Both the statement are true |
| D. | Both the statements are false |
| Answer» B. Only statement 2 is true | |
| 29. |
The gates G1 and G2 in the figure have propagation delays of 10 n sec. and 20 n sec. respectively. If the input Vi makes an output change from logic 0 to 1 at time t = t0 then the output wavefrom V0 is |
| A. | [A]. |
| B. | [B]. |
| C. | [C]. |
| D. | [D]. |
| Answer» E. | |
| 30. |
For the ring oscillator shown in the figure, the propagation delay of each inverter is 100 pico sec. What is the fundamental frequency of the oscillator output __________ |
| A. | 10 MHz |
| B. | 100 MHz |
| C. | 1 GHz |
| D. | 2 GHz |
| Answer» E. | |
| 31. |
What will be FSV in 2 bit BCD D/A converter is a weighted resistor type with ER = 1V, R = 1 MΩ and Rf = 10KΩ |
| A. | 0.99 V |
| B. | 0.9 V |
| C. | 0.1 V |
| D. | 0 |
| Answer» B. 0.9 V | |
| 32. |
A 2 bit BCD D/A converter is a weighted resistor type with ER = 1V, R = 1 MΩ and Rf = 10KΩ then Resolution in percent and volt is __________ . |
| A. | 1%, 1 mv |
| B. | 10%, 10 mv |
| C. | 10%, 1 mv |
| D. | 1%, 10 mv |
| Answer» E. | |
| 33. |
A 3 stage Johnson counter (ring) shown in figure is clocked at a constant frequency of fc from the starting state of Q0 Q1 Q2 = 101. The frequency of output Q0 Q1 Q2 will be |
| A. | [A]. |
| B. | [B]. |
| C. | [C]. |
| D. | [D]. |
| Answer» D. [D]. | |
| 34. |
An XOR gate with 6 variables is as follows A ⊕ B ⊕ C ⊕ D ⊕ E ⊕ F. The number of minterms in the Boolean expression is |
| A. | 6 |
| B. | 12 |
| C. | 64 |
| D. | 32 |
| Answer» E. | |
| 35. |
The Boolean expression A ⊕ B is equivalent to |
| A. | AB + AB |
| B. | AB + AB |
| C. | B |
| D. | A |
| Answer» C. B | |
| 36. |
An 8 bit DAC has a full scale output of 2 mA and full scale error of ± 0.5%. If input is 10000000 the range of outputs is |
| A. | 994 to 1014 μA |
| B. | 990 to 1020 μA |
| C. | 800 to 1200 μA |
| D. | none of the above |
| Answer» B. 990 to 1020 μA | |
| 37. |
In the given figure, the flip flop is |
| A. | negative edge triggered |
| B. | positive edge triggered |
| C. | level triggered |
| D. | either (a) or (c) |
| Answer» B. positive edge triggered | |
| 38. |
For the DAC in the given figure VO= |
| A. | 10 V |
| B. | 5 V |
| C. | 4 V |
| D. | 8 V |
| Answer» B. 5 V | |
| 39. |
Inverter 74 LS04 has following specifications I0H max = - 0.4 mA, I0L max = 8 mA, IIH max = 20 μA, IIL max = 0.1 mAThe fan out of this inverter is |
| A. | 10 |
| B. | 20 |
| C. | 60 |
| D. | 100 |
| Answer» C. 60 | |
| 40. |
A 10 bit ADC with a full scale output voltage of 10.24 V is to be designed to have ± LSB/2 accuracy. If ADC is calibrated at 25°C, the maximum net temperature coefficient of ADC should not exceed |
| A. | ± 200 μV/°C |
| B. | ± 400 μV/°C |
| C. | ± 600 μV/°C |
| D. | ± 800 μV/°C |
| Answer» B. ± 400 μV/°C | |
| 41. |
A dynamic RAM cell which holds 5 V has to be refreshed every 20 ms so that the stored voltage does not fall by more than 0.5 V. If the cell has a constant discharge current of 0.1 pA, the storage capacitance of cell is |
| A. | 4 x 10-6 F |
| B. | 4 x 10-9 F |
| C. | 4 x 10-12 F |
| D. | 4 x 10-15 F |
| Answer» E. | |
| 42. |
A 12 bit ADC is operating with 1 μs clock period. Total conversion time is 14 μs. ADC is |
| A. | flash type |
| B. | counting type |
| C. | integrating type |
| D. | successive approximation type |
| Answer» D. successive approximation type | |
| 43. |
In the given figure shows a 3 bit shift register using TTL flip flops. Initially all the flip flops are set to 0 state. After 8 clock pulses |
| A. | A = 1, B = 1, C = 1 |
| B. | A = 1, B = 1, C = 0 |
| C. | A = 0, B = 1, C = 1 |
| D. | A = 0, B = 0, C = 1 |
| Answer» B. A = 1, B = 1, C = 0 | |
| 44. |
Consider the following statements: A multiplier selects one of the several inputs and steers it to the outputroutes the data from a single input to many outputsconverts parallel data into serial datais a combinational circuit On the above statements which are correct? |
| A. | 1, 2, 4 |
| B. | 2, 3, 4 |
| C. | 1, 3, 4 |
| D. | 1, 2, 3 |
| Answer» D. 1, 2, 3 | |
| 45. |
The logic circuit of the given figure is equivalent to |
| A. | [A]. |
| B. | [B]. |
| C. | [C]. |
| D. | [D]. |
| Answer» D. [D]. | |
| 46. |
Symmetrical square wave of time period 100 μs can be obtained from square wave of time period 10 μs by using |
| A. | divide by 5 circuit |
| B. | divide by 2 circuit |
| C. | divide by 5 circuit followed by divide by 2 circuit |
| D. | BCD counter |
| Answer» D. BCD counter | |
| 47. |
The inputs to a NAND gate are as shown in the given figure. The waveform of output is |
| A. | [A]. |
| B. | [B]. |
| C. | [C]. |
| D. | [D]. |
| Answer» B. [B]. | |
| 48. |
In the given figure RC = RL = 1 kΩ, then V0 = |
| A. | 5 V |
| B. | 2.5 V |
| C. | 1 V |
| D. | 0 V |
| Answer» C. 1 V | |
| 49. |
A DAC has full scale output of 5 V. If accuracy is ± 0.2% the maximum error for an output of 1 V is |
| A. | 5 mV |
| B. | 10 mV |
| C. | 2 mV |
| D. | 20 mV |
| Answer» C. 2 mV | |
| 50. |
Which of the circuits in the given figure that converts JK flip flop to T flip flop? |
| A. | [A]. |
| B. | [B]. |
| C. | [C]. |
| D. | [D]. |
| Answer» B. [B]. | |