MCQOPTIONS
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MCQOPTIONS
This section includes 657 Mcqs, each offering curated multiple-choice questions to sharpen your Testing Subject knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Logic circuits that are designated as buffers, drivers or buffers/drivers are designed to have: |
| A. | a greater current/voltage capability than an ordinary logic circuit |
| B. | greater input current/voltage capability than an ordinary logic circuit |
| C. | a smaller output current/voltage capability than an ordinary logic |
| D. | greater the input and output current/voltage capability than an ordinary logic circuit |
| Answer» B. greater input current/voltage capability than an ordinary logic circuit | |
| 2. |
The primary purpose of a three-state buffer is usually |
| A. | to provide isolation between the input device and the data bus |
| B. | to provide the sink or source current required by any device connected to its output without loading down the output device |
| C. | temporary data storage |
| D. | to control data flow |
| Answer» B. to provide the sink or source current required by any device connected to its output without loading down the output device | |
| 3. |
What is the difference between a ring shift counter and a Johnson shift counter? |
| A. | there is no difference |
| B. | a ring is faster |
| C. | the feedback is reversed |
| D. | the johnson is faster |
| Answer» D. the johnson is faster | |
| 4. |
An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output? |
| A. | 1.67 s |
| B. | 26.67 s |
| C. | 26.7 ms |
| D. | 267 ms |
| Answer» C. 26.7 ms | |
| 5. |
How is an strobe signal used when serially loading a shift register? |
| A. | to turn the register on and off |
| B. | to control the number of clocks |
| C. | to determine which output qs are used |
| D. | to determine the ffs that will be used |
| Answer» C. to determine which output qs are used | |
| 6. |
How many clock pulses will be required to completely load serially a 5-bit shift register? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» E. | |
| 7. |
A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing |
| A. | 1101 |
| B. | 0111 |
| C. | 0001 |
| D. | 1110 |
| Answer» C. 0001 | |
| 8. |
A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit? |
| A. | ring shift |
| B. | clock |
| C. | johnson |
| D. | binary |
| Answer» B. clock | |
| 9. |
A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains |
| A. | 0000 |
| B. | 1111 |
| C. | 0111 |
| D. | 1000 |
| Answer» D. 1000 | |
| 10. |
An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of |
| A. | 16 us |
| B. | 8 us |
| C. | 4 us |
| D. | 2 us |
| Answer» D. 2 us | |
| 11. |
Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first) |
| A. | 1100 |
| B. | 0011 |
| C. | 0000 |
| D. | 1111 |
| Answer» D. 1111 | |
| 12. |
With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in |
| A. | 4 μs |
| B. | 40 μs |
| C. | 400 μs |
| D. | 40 ms |
| Answer» C. 400 μs | |
| 13. |
The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains |
| A. | 01110 |
| B. | 00001 |
| C. | 00101 |
| D. | 00110 |
| Answer» D. 00110 | |
| 14. |
A shift register that will accept a parallel input or a bidirectional serial load and internal shift features is called as? |
| A. | tristate |
| B. | end around |
| C. | universal |
| D. | conversion |
| Answer» D. conversion | |
| 15. |
Another way to connect devices to a shared data bus is to use a |
| A. | circulating gate |
| B. | transceiver |
| C. | bidirectional encoder |
| D. | strobed latch |
| Answer» C. bidirectional encoder | |
| 16. |
What is the function of a buffer circuit? |
| A. | to provide an output that is inverted from that on the input |
| B. | to provide an output that is equal to its input |
| C. | to clean up the input |
| D. | to clean up the output |
| Answer» C. to clean up the input | |
| 17. |
A 74HC195 4-bit parallel access shift register can be used for |
| A. | serial in/serial out operation |
| B. | serial in/parallel out operation |
| C. | parallel in/serial out operation |
| D. | all of the mentioned |
| Answer» E. | |
| 18. |
What is the preset condition for a ring shift counter? |
| A. | all ffs set to 1 |
| B. | all ffs cleared to 0 |
| C. | a single 0, the rest 1 |
| D. | a single 1, the rest 0 |
| Answer» E. | |
| 19. |
What is the difference between a shift-right register and a shift-left register? |
| A. | there is no difference |
| B. | the direction of the shift |
| C. | propagation delay |
| D. | the clock input |
| Answer» C. propagation delay | |
| 20. |
What is a transceiver circuit? |
| A. | a buffer that transfers data from input to output |
| B. | a buffer that transfers data from output to input |
| C. | a buffer that can operate in both directions |
| D. | a buffer that can operate in one direction |
| Answer» D. a buffer that can operate in one direction | |
| 21. |
Ring shift and Johnson counters are |
| A. | synchronous counters |
| B. | asynchronous counters |
| C. | true binary counters |
| D. | synchronous and true binary counters |
| Answer» B. asynchronous counters | |
| 22. |
What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops? |
| A. | 0 to 2n |
| B. | 0 to 2n + 1 |
| C. | 0 to 2n – 1 d) 0 to 2n+1/2 |
| Answer» D. | |
| 23. |
State transition happens                in every clock cycle. |
| A. | once |
| B. | twice |
| C. | thrice |
| D. | four times |
| Answer» B. twice | |
| 24. |
In FSM diagram what does circle represent? |
| A. | change of state |
| B. | state |
| C. | output value |
| D. | initial state |
| Answer» C. output value | |
| 25. |
In the FSM diagram, what does the information below the line in the circle represent? |
| A. | change of state |
| B. | state |
| C. | output value |
| D. | initial state |
| Answer» D. initial state | |
| 26. |
Moore machine has                    states than a mealy machine. |
| A. | fewer |
| B. | more |
| C. | equal |
| D. | negligible |
| Answer» C. equal | |
| 27. |
Moore machine output is synchronous. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 28. |
Finite state machines are combinational logic systems. |
| A. | true |
| B. | false |
| Answer» C. | |
| 29. |
In four bit dynamic shift register output is obtained |
| A. | parallel output at inverters 1, 3, 5, 7 |
| B. | parallel output at inverters 1, 5, 8 |
| C. | parallel output at all inverters |
| D. | parallel output at inverter 2, 4, 6, 8 |
| Answer» E. | |
| 30. |
In a four bit dynamic shift register basic nMOS transistor or inverters are connected in |
| A. | series |
| B. | cascade |
| C. | parallel |
| D. | series and parallel |
| Answer» C. parallel | |
| 31. |
Register cell consists of |
| A. | inverter |
| B. | pass transistor |
| C. | inverter & pass transistor |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 32. |
Non inverting dynamic register storage cell consists of                    transistors for nMOS and                    for CMOS. |
| A. | six, eight |
| B. | eight, six |
| C. | five, six |
| D. | six, five |
| Answer» B. eight, six | |
| 33. |
As the temperature is increased, storage time |
| A. | halved |
| B. | doubled |
| C. | does not change |
| D. | tripled |
| Answer» B. doubled | |
| 34. |
                       is used to drive high capacitance load. |
| A. | single polar capability |
| B. | bipolar capability |
| C. | tripolar capability |
| D. | bi and tri polar capability |
| Answer» C. tripolar capability | |
| 35. |
Which are easier to design? |
| A. | clocked circuits |
| B. | asynchronous sequential circuits |
| C. | clocked circuits with buffer |
| D. | asynchronous sequential circuits with buffers |
| Answer» B. asynchronous sequential circuits | |
| 36. |
How many OR gates are required for an octal-to-binary encoder? |
| A. | 3 |
| B. | 2 |
| C. | 8 |
| D. | 10 |
| Answer» B. 2 | |
| 37. |
How many OR gates are required for a Decimal-to-bcd encoder? |
| A. | 2 |
| B. | 10 |
| C. | 3 |
| D. | 4 |
| Answer» E. | |
| 38. |
Can an encoder be a transducer? |
| A. | yes |
| B. | no |
| C. | may or may not be |
| D. | both are not even related slightly |
| Answer» B. no | |
| 39. |
What is data routing in a multiplexer? |
| A. | it spreads the information to the control unit |
| B. | it can be used to route data from one of several source to destination |
| C. | it is an application of multiplexer |
| D. | both it can be used to route data and it is an application of multiplexer |
| Answer» E. | |
| 40. |
If enable input is high then the multiplexer is |
| A. | enable |
| B. | disable |
| C. | saturation |
| D. | high impedance |
| Answer» C. saturation | |
| 41. |
The inputs/outputs of an analog multiplexer/demultiplexer are |
| A. | bidirectional |
| B. | unidirectional |
| C. | even parity |
| D. | binary-coded decimal |
| Answer» B. unidirectional | |
| 42. |
Which of the following circuit can be used as parallel to serial converter? |
| A. | multiplexer |
| B. | demultiplexer |
| C. | decoder |
| D. | digital counter |
| Answer» B. demultiplexer | |
| 43. |
A combinational circuit that selects one from many inputs are |
| A. | encoder |
| B. | decoder |
| C. | demultiplexer |
| D. | multiplexer |
| Answer» E. | |
| 44. |
4 to 1 MUX would have |
| A. | 2 inputs |
| B. | 3 inputs |
| C. | 4 inputs |
| D. | 5 inputs |
| Answer» D. 5 inputs | |
| 45. |
Comparators are used in |
| A. | memory |
| B. | cpu |
| C. | motherboard |
| D. | hard drive |
| Answer» C. motherboard | |
| 46. |
How many select lines would be required for an 8-line-to-1-line multiplexer? |
| A. | 2 |
| B. | 4 |
| C. | 8 |
| D. | 3 |
| Answer» E. | |
| 47. |
6 MULTIPLEXER |
| A. | to apply vcc |
| B. | to connect ground |
| C. | to active the entire chip |
| D. | to active one half of the chip |
| Answer» D. to active one half of the chip | |
| 48. |
A D flip-flop is used in a 4-bit serial adder, why? |
| A. | it is used to invert the input of the full adder |
| B. | it is used to store the output of the full adder |
| C. | it is used to store the carry output of the full adder |
| D. | it is used to store the sum output of the full adder |
| Answer» D. it is used to store the sum output of the full adder | |
| 49. |
If minuend = 0, subtrahend = 1 and borrow input = 1 in a full subtractor then the borrow output will be |
| A. | 0 |
| B. | 1 |
| C. | floating |
| D. | high impedance |
| Answer» C. floating | |
| 50. |
What is ripple carry adder? |
| A. | the carry output of the lower order stage is connected to the carry input of the next higher order stage |
| B. | the carry input of the lower order stage is connected to the carry output of the next higher order stage |
| C. | the carry output of the higher order stage is connected to the carry input of the next lower order stage |
| D. | the carry input of the higher order stage is connected to the carry output of the lower order stage |
| Answer» B. the carry input of the lower order stage is connected to the carry output of the next higher order stage | |