MCQOPTIONS
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MCQOPTIONS
This section includes 17 Mcqs, each offering curated multiple-choice questions to sharpen your Vlsi knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Multiple output domino logic has |
| A. | two cell manchester carry chain |
| B. | three cell manchester carry chain |
| C. | four cell manchester carry chain |
| D. | four cell manchester carry look ahead |
| Answer» D. four cell manchester carry look ahead | |
| 2. |
For carry skip adder, the minimum total propogation delay can be obtained when m is |
| A. | sqrt(nk1/k2) |
| B. | sqrt(2nk1/k2) |
| C. | sqrt(2k1/nk2) |
| D. | sqrt(nk1k2/2) |
| Answer» C. sqrt(2k1/nk2) | |
| 3. |
Adder using _______ technology can be used for speed improvement. |
| A. | CMOS |
| B. | BiCMOS |
| C. | nMOS |
| D. | pMOS |
| Answer» C. nMOS | |
| 4. |
In adders, the previous carry can also be given by |
| A. | propagate signal pk |
| B. | generate signal gk |
| C. | pk and gk |
| D. | sk |
| Answer» D. sk | |
| 5. |
Design gives a detailed |
| A. | logic circuit design |
| B. | topology of communication |
| C. | colour codes of the layers |
| D. | functions of layers |
| Answer» C. colour codes of the layers | |
| 6. |
ADDER_USING______TECHNOLOGY_CAN_BE_USED_FOR_SPEED_IMPROVEMENT?$ |
| A. | CMOS |
| B. | BiCMOS |
| C. | nMOS |
| D. | pMOS |
| Answer» C. nMOS | |
| 7. |
Multiple output domino logic has$ |
| A. | two cell manchester carry chain |
| B. | three cell manchester carry chain |
| C. | four cell manchester carry chain |
| D. | four cell manchester carry look ahead |
| Answer» D. four cell manchester carry look ahead | |
| 8. |
For carry skip adder, the minimum total propogation delay can be obtained when m is$ |
| A. | sqrt (nk1/k2) |
| B. | sqrt (2nk1/k2) |
| C. | sqrt (2k1/nk2) |
| D. | sqrt (nk1k2/2) |
| Answer» C. sqrt (2k1/nk2) | |
| 9. |
In adders, the previous carry can also be given b? |
| A. | propogate signal pk |
| B. | generate signal gk |
| C. | pk and gk |
| D. | sk |
| Answer» D. sk | |
| 10. |
Which design is preferred in n-bit adder? |
| A. | many pass transistors in series |
| B. | many pass transistors with suitable buffer |
| C. | many pass transistors without suitable buffer |
| D. | many pass transistors in parallel |
| Answer» C. many pass transistors without suitable buffer | |
| 11. |
What is the sum and carry if the two bit number is 1 1 and the previous carry is 0? |
| A. | 0,0 |
| B. | 0,1 |
| C. | 1,0 |
| D. | 1,1 |
| Answer» C. 1,0 | |
| 12. |
The shifter must be connected to |
| A. | 2-shift data line |
| B. | 2-shift control line |
| C. | 4-shift data line |
| D. | 4-shift control line |
| Answer» E. | |
| 13. |
In the adder, sum is stored in |
| A. | series |
| B. | cascade |
| C. | parallel |
| D. | registers |
| Answer» D. registers | |
| 14. |
Good design system has regularity in the range of |
| A. | 25-50 |
| B. | 50-75 |
| C. | 50-100 |
| D. | 25-50 |
| Answer» D. 25-50 | |
| 15. |
Regularity is the ratio of |
| A. | total transistors in the chip to total transistors that must be designed in detail |
| B. | total transistors that must be designed in detail to total transistors in chip |
| C. | total transistors to total components |
| D. | total charge storage components to charge dissipating components |
| Answer» B. total transistors that must be designed in detail to total transistors in chip | |
| 16. |
To minimize the design effort, regularity should be |
| A. | low |
| B. | high |
| C. | very low |
| D. | very high |
| Answer» C. very low | |
| 17. |
Design gives the detailed |
| A. | logic circuit design |
| B. | topology of communication |
| C. | colour codes of the layers |
| D. | functions of layers |
| Answer» C. colour codes of the layers | |