MCQOPTIONS
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MCQOPTIONS
This section includes 36 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Organization knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Consider the following code sequence having five instructions I1 to I5. Each of these instructions has the following format.OP Ri, Rj, RkWhere operation OP is performed on contents of registers Rj and Rk and the result is stored in register RiI1: ADD R1, R2, R3I2: MUL R7, R1, R3I3: SUB R4, R1, R5I4: ADD R3, R2, R4I5: MUL R7, R8, R9Consider the following three statements.S1: There is an anti-dependence between instructions I2 and I5S2: There is an anti-dependence between instructions I2 and I4S3: Within an instruction pipeline an anti-dependence always creates one or more stallsWhich one of the above statements is/are correct? |
| A. | Only S1 is true |
| B. | Only S2 is true |
| C. | Only S1 and S3 are true |
| D. | Only S2 and S3 are true |
| Answer» C. Only S1 and S3 are true | |
| 2. |
A non-pipeline system takes 50ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of 10ns. Determine approximately the speedup ratio of the pipeline for 500 tasks. |
| A. | 6 |
| B. | 4.95 |
| C. | 5.7 |
| D. | 5.5 |
| Answer» C. 5.7 | |
| 3. |
Pipelining increases ______ of the processor. |
| A. | Throughput |
| B. | Storage |
| C. | Predictivity |
| D. | Latency |
| Answer» B. Storage | |
| 4. |
Consider a 5-segment pipeline with a clock cycle time 20ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute 100 instructions. (if an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline) |
| A. | 5 |
| B. | 4.03 |
| C. | 4.81 |
| D. | 4.17 |
| Answer» C. 4.81 | |
| 5. |
In microprocessors, the IC (instruction cycle), FC (fetch cycle) and EC (execution cycle) are related as |
| A. | IC = FC - EC |
| B. | IC = FC + EC |
| C. | IC = FC + 2EC |
| D. | EC = IC + FC |
| Answer» C. IC = FC + 2EC | |
| 6. |
A data-driven machine is one that executes an instruction if the needed data is available. The physical ordering of the code listing does not dictate the course of execution. Consider the following pseudo-code1) Multiply E by 0.5 to get F2) Add A and B to get E3) Add B with 0.5 to get D4) Add E and F to get G5) Add A with 10.5 to get CAssume A, B, C are already assigned values and the desired output is G Which of the following sequence of execution is valid? |
| A. | B C, D, A, E |
| B. | C, B, E, A, D |
| C. | A, B, C, D, E |
| D. | E, D, C, B, A |
| Answer» C. A, B, C, D, E | |
| 7. |
Consider a control unit generating the control signals. These control signals are divided into five mutually exclusive groups as shown below:Groups G1 G1 G1 G1 G1Control Signals 3 7 10 12 2How many bits are saved using the Vertical Micro-programmed instead of Horizontal Micro-programmed control unit? |
| A. | 14 |
| B. | 34 |
| C. | 20 |
| D. | None |
| Answer» D. None | |
| 8. |
A particular parallel program computation requires 100 sec when executed on a single processor. If 40% of this computation is inherently sequential (i.e. will not benefit from additional processors), then theoretically best possible elapsed times of this program running with 2 and 4 processors, respectively, are |
| A. | 20 sec and 10 sec |
| B. | 30 sec and 15 sec |
| C. | 50 sec and 25 sec |
| D. | 70 sec and 55 sec |
| Answer» E. | |
| 9. |
Execute Cycle of Computer is |
| A. | Longer than instruction cycle |
| B. | Equal to Instruction Cycle |
| C. | Part of Instruction Cycle |
| D. | None of these |
| Answer» D. None of these | |
| 10. |
If instruction X tries to modify some data before it is written by instruction (X-1), it can result in a ________ hazard. |
| A. | RAR |
| B. | RAW |
| C. | WAR |
| D. | WAW |
| Answer» E. | |
| 11. |
Consider the following processor (ns stands for nanoseconds). Assume that the pipeline registers have zero latency.P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns.P2: Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns.P3: Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 nsP4: Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 nsWhich processor has the highest peak clock frequency? |
| A. | P1 |
| B. | P2 |
| C. | P3 |
| D. | P4 |
| Answer» D. P4 | |
| 12. |
Fill in the blank in context of software system architecture:In __________ architecture, the processing of the data in a system is organized so that each processing component is discrete and carries out one type of data transformation. The data flows from one component to another for processing. |
| A. | Pipe and filter |
| B. | Repository |
| C. | Layered |
| D. | Client-Server |
| Answer» B. Repository | |
| 13. |
In a real-time system, the simplest scheme that allows the operating system to allocate memory to two processes simultaneously is _______. |
| A. | Over lays |
| B. | Pipeline |
| C. | Swapping |
| D. | None of the above |
| Answer» C. Swapping | |
| 14. |
One instruction tries to write an operand before it is written by previous instruction. This may lead to a dependency called |
| A. | True dependency |
| B. | Anti-dependency |
| C. | Output Dependency |
| D. | Control hazard |
| Answer» D. Control hazard | |
| 15. |
Consider the following sequence of micro-operations.MBR ← PCMAR ← XPC ← YMemory ← MBRWhich one of the following is a possible operation performed by this sequence? |
| A. | Instruction fetch |
| B. | Operand fetch |
| C. | Conditional branch |
| D. | Initiation of interrupt service |
| Answer» E. | |
| 16. |
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I1, I2, I3, …, I12 is executed in this pipelined processor.Instruction I4 is the only branch instruction and its branch target is I9. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is |
| A. | 132 |
| B. | 165 |
| C. | 176 |
| D. | 328 |
| Answer» C. 176 | |
| 17. |
Considering equal processing time for each segment, speed-up S achieved by a K-segment instruction pipeline operating on straight sequence of N instructions is given by: |
| A. | \(S=\frac{K(N-K)}{K+N-1}\) |
| B. | \(S=\frac{K+N}{KN}\) |
| C. | \(S=\frac{K(K+1)}{(K+1)N}\) |
| D. | \(S=\frac{KN}{K+N-1}\) |
| Answer» E. | |
| 18. |
In the context of an instruction set, orthogonality indicates that other elements of an instruction are ______ of/by the opcode. |
| A. | independent |
| B. | dependent |
| C. | determined |
| D. | executed |
| Answer» B. dependent | |
| 19. |
A non-pipelined CPU has 12 general purpose registers (R0, R1, R2,….R12). Following operations are supportedADD Ra, Rb, Rr Add Ra to Rb and store the result in RrMUL Ra, Rb, Rr Multiply Ra to Rb and store the result in RrMUL operations takes two clock cycles, ADD takes one clock cycle.Calculate minimum number of clock cycles required to compute the value of the expression XY + XYZ + YZ. The variables X, Y, Z are initially available in registers R0, R1 and R2 and contents of these registers must not be modified. |
| A. | 5 |
| B. | 6 |
| C. | 7 |
| D. | 8 |
| Answer» C. 7 | |
| 20. |
Consider the following data path diagram. Consider an instruction: R0 ← R1 + R2. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts r and w indicate read and write operations, respectively.1. R2r, TEMP1f, ALUadd, TEMP2w2. R1r, TEMP1w3. PCr, MARw, MEMr4. TEMP2r, R0w5. MDRr, IRwWhich one of the following is the correct order of execution of the above steps? |
| A. | 2, 1, 4, 5, 3 |
| B. | 1, 2, 4, 3, 5 |
| C. | 3, 5, 2, 1, 4 |
| D. | 3, 5, 1, 2, 4 |
| Answer» D. 3, 5, 1, 2, 4 | |
| 21. |
If computer A has cycle ta = 250ps and cpl (cycles/inst) = 2.0 and computer B has cycle tb = 500ps and cpl = 1.2 then: |
| A. | Computer B is 1.2 faster than A |
| B. | Computer B is 2 times faster than B |
| C. | Computer B is 2 times faster than A |
| D. | Computer A is 1.2 times faster than B |
| Answer» E. | |
| 22. |
For a pipelines CPU with a single ALU, consider the following :A. The j + 1st instruction uses the result of jth instruction as an operandB. Conditional jump instructionC. jth and j + 1st instructions require ALU at the same timeWhich one of the above causes a hazard? |
| A. | A and B only |
| B. | B and C only |
| C. | B only |
| D. | A, B, C |
| Answer» E. | |
| 23. |
Pipelining1. Reduces clock period of long combinational operations.2. Allows large combinational functions to be broken down into pieces whose delays are balanced with the rest of the system components. |
| A. | 1 only |
| B. | 2 only |
| C. | Both 1 and 2 |
| D. | Neither 1 nor 2 |
| Answer» D. Neither 1 nor 2 | |
| 24. |
Consider a non-pipelined processor with a clock rate of 2.5 GHz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 GHz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is |
| A. | 3.2 |
| B. | 3.0 |
| C. | 2.2 |
| D. | 2.0 |
| Answer» B. 3.0 | |
| 25. |
How many characters per second (7 bits + 1 parity) can be transmitted over a 2400 bps line if the transfer is asynchronous (1 start and 1 stop bit)? |
| A. | 240 |
| B. | 250 |
| C. | 275 |
| D. | 300 |
| Answer» B. 250 | |
| 26. |
Match List-I with List-II and select the correct answer using the code given below the lists:List-IList-II a. Pipelined ALU i. RISC b. Simpler compiler ii. CISC c. Separate data and instruction caches iii. Mixed RISC-CISC d. Lesser cycles per instruction |
| A. | a - iii, b - ii, c - iii, d - i |
| B. | a - i, b - ii, c - iii, d - iii |
| C. | a - iii, b - iii, c - ii, d - i |
| D. | a - iii, b - iii, c - iii, d - i |
| Answer» B. a - i, b - ii, c - iii, d - iii | |
| 27. |
THE_CONTENTION_FOR_THE_USAGE_OF_A_HARDWARE_DEVICE_IS_CALLED_______?$ |
| A. | Structural hazard |
| B. | Stalk |
| C. | Deadlock |
| D. | None of the mentioned |
| Answer» B. Stalk | |
| 28. |
The_situation_wherein_the_data_of_operands_are_not_available_is_called_______$ |
| A. | Data hazard |
| B. | Stock |
| C. | Deadlock |
| D. | Structural hazard |
| Answer» B. Stock | |
| 29. |
The periods of time when the unit is idle is called as ____? |
| A. | Stalls |
| B. | Bubbles |
| C. | Hazards |
| D. | Both Stalls and Bubbles |
| Answer» E. | |
| 30. |
To increase the speed of memory access in pipelining, we make use of _______ |
| A. | Special memory locations |
| B. | Special purpose registers |
| C. | Cache |
| D. | Buffers |
| Answer» D. Buffers | |
| 31. |
If a unit completes its task before the allotted time period, then _______ |
| A. | It’ll perform some other task in the remaining time |
| B. | Its time gets reallocated to a different task |
| C. | It’ll remain idle for the remaining time |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |
| 32. |
In pipelining the task which requires the least time is performed first. |
| A. | True |
| B. | False |
| Answer» C. | |
| 33. |
Each stage in pipelining should be completed within ____ cycle. |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» B. 2 | |
| 34. |
The fetch and execution cycles are interleaved with the help of ________ |
| A. | Modification in processor architecture |
| B. | Clock |
| C. | Special unit |
| D. | Control unit |
| Answer» C. Special unit | |
| 35. |
The pipelining process is also called as ______ |
| A. | Superscalar operation |
| B. | Assembly line operation |
| C. | Von Neumann cycle |
| D. | None of the mentioned |
| Answer» C. Von Neumann cycle | |
| 36. |
______ have been developed specifically for pipelined systems. |
| A. | Utility software |
| B. | Speed up utilities |
| C. | Optimizing compilers |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |