Consider the following processor (ns stands for nanoseconds). Assume that the pipeline registers have zero latency.P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns.P2: Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns.P3: Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 nsP4: Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 nsWhich processor has the highest peak clock frequency?

Consider the following processor (ns stands for nanoseconds). Assume t

1.	Consider the following processor (ns stands for nanoseconds). Assume that the pipeline registers have zero latency.P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns.P2: Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns.P3: Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 nsP4: Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 nsWhich processor has the highest peak clock frequency?
A.	P1
B.	P2
C.	P3
D.	P4
Answer» D. P4

Discussion

No Comment Found

Related MCQs

Consider the following code sequence having five instructions I1 to I5. Each of these instructions has the following format.OP Ri, Rj, RkWhere operation OP is performed on contents of registers Rj and Rk and the result is stored in register RiI1: ADD R1, R2, R3I2: MUL R7, R1, R3I3: SUB R4, R1, R5I4: ADD R3, R2, R4I5: MUL R7, R8, R9Consider the following three statements.S1: There is an anti-dependence between instructions I2 and I5S2: There is an anti-dependence between instructions I2 and I4S3: Within an instruction pipeline an anti-dependence always creates one or more stallsWhich one of the above statements is/are correct?
A non-pipeline system takes 50ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of 10ns. Determine approximately the speedup ratio of the pipeline for 500 tasks.
Pipelining increases ______ of the processor.
Consider a 5-segment pipeline with a clock cycle time 20ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute 100 instructions. (if an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline)
In microprocessors, the IC (instruction cycle), FC (fetch cycle) and EC (execution cycle) are related as
A data-driven machine is one that executes an instruction if the needed data is available. The physical ordering of the code listing does not dictate the course of execution. Consider the following pseudo-code1) Multiply E by 0.5 to get F2) Add A and B to get E3) Add B with 0.5 to get D4) Add E and F to get G5) Add A with 10.5 to get CAssume A, B, C are already assigned values and the desired output is G Which of the following sequence of execution is valid?
Consider a control unit generating the control signals. These control signals are divided into five mutually exclusive groups as shown below:Groups G1 G1 G1 G1 G1Control Signals 3 7 10 12 2How many bits are saved using the Vertical Micro-programmed instead of Horizontal Micro-programmed control unit?
A particular parallel program computation requires 100 sec when executed on a single processor. If 40% of this computation is inherently sequential (i.e. will not benefit from additional processors), then theoretically best possible elapsed times of this program running with 2 and 4 processors, respectively, are
Execute Cycle of Computer is
If instruction X tries to modify some data before it is written by instruction (X-1), it can result in a ________ hazard.

Discussion

No Comment Found

Related MCQs

Reply to Comment